公开(公告)号：EP1643651A1

公开(公告)日：2006-04-05

申请号：EP04425727.7

申请日：2004-09-29

Applicant: STMicroelectronics S.r.l.

Inventor： Bruno, Angela ,  Cali', Giovanni ,  Palleschi, Antonio

IPC: H03M1/74

CPC classification number: H03M1/1061 ,  H03M1/745

Abstract: The present invention describes an apparatus for the conversion of a digital input signal (Sx) into a required analogic output signal (Idac). The apparatus comprises first circuit means (1, 5) having said digital input signal (Sx) that is representative of the required output signal (Idac) and suitable for producing a first signal (Imain) on an output line (2) and second circuit means (3, 20) suitable for supplying a second signal (Itrim) on said output line (2) in reply to a further digital signal (Dult). The further digital signal (Dult) is function of external variables (Var) and the union of said first (Imain) and said second (Itrim) signal on said output line (2) forms the required analogic output signal (Idac).

Abstract translation: 本发明描述了一种用于将数字输入信号（Sx）转换成所需的模拟输出信号（Idac）的装置。 该装置包括具有表示所需输出信号（Idac）的所述数字输入信号（Sx）并且适合于在输出线（2）和第二电路（2）上产生第一信号（Imain）的第一电路装置（1,5） 适于在所述输出线（2）上提供第二信号（Itrim）以响应另一数字信号（Dult）的装置（3,20）。 另外的数字信号（Dult）是外部变量（Var）的函数，并且所述输出线（2）上的所述第一（Imain）和所述第二（Itrim）信号的并集形成所需的模拟输出信号（Idac）。

公开(公告)号：EP1643651B1

公开(公告)日：2008-03-05

申请号：EP04425727.7

申请日：2004-09-29

Applicant: STMicroelectronics S.r.l.

Inventor： Bruno, Angela ,  Cali', Giovanni ,  Palleschi, Antonio

IPC: H03M1/74

CPC classification number: H03M1/1061 ,  H03M1/745

公开(公告)号：EP1643649A1

公开(公告)日：2006-04-05

申请号：EP04425728.5

申请日：2004-09-29

Applicant: STMicroelectronics S.r.l.

Inventor： Bruno, Angela ,  Cali', Giovanni ,  Palleschi, Antonio

IPC: H03L7/197

CPC classification number: H03L7/1978 ,  H03L7/0891

Abstract: The present invention refers to a phase-locked loop comprising an oscillator (10), a phase detector (30) having in input a signal (fr) proportional to the signal in output from the oscillator, a charge pump (50) having in input the signal in output from said phase detector (30), a filter (60) coupled with the charge pump (50), a voltage controlled oscillator (70) and a fractional frequency divider (40). The voltage controlled oscillator (70) is coupled with the filter (60) and sends an output signal (fo) to the fractional frequency divider (40). The fractional frequency divider (40) is adapted to sending an output signal (fv) to the phase detector (30). The phase-locked loop comprises a digital-analogical converter (100) coupled with the charge pump (50) and with the filter (60), an accumulator (80) coupled with the fractional frequency divider (40) and with the digital-analogical converter (100). The fractional frequency divider (40) comprises a prescaler (41) adapted to dividing the signal in input (fo) by a whole number P or by an integer number P+1 and the fractional frequency divider (40) emits a first representative signal (MC) of the division by P or by P+1 of the prescaler (41). The first signal (MC) is in input to the digital-analogical converter (100) so that the signal (Idac) in output from the digital-analogical converter (100) is aligned with the first signal (MC). The phase-locked loop comprises a circuitry (90) coupled to the digital-analogical converter (100) and to the prescaler (41) to synchronize the signal (Idac) in output from the digital-analogical converter (100) with the signal in output (Prout) from the prescaler (41).

Abstract translation: 本发明涉及一种锁相环，包括振荡器（10），相位检测器（30），输入端具有与振荡器的输出信号成比例的信号（fr），具有输入的电荷泵（50） 来自所述相位检测器（30）的输出信号，与所述电荷泵（50）耦合的滤波器（60），压控振荡器（70）和分数分频器（40）。 压控振荡器（70）与滤波器（60）耦合，并将输出信号（fo）发送到分数分频器（40）。 分数分频器（40）适于向相位检测器（30）发送输出信号（fv）。 锁相环包括与电荷泵（50）和滤波器（60）耦合的数模转换器（100），与分数分频器（40）耦合的累加器（80）和数字模拟 转换器（100）。 分数分频器（40）包括预分频器（41），适于将输入（fo）中的信号除以整数P或整数P + 1，分数分频器（40）发射第一代表信号 MC）除以P或P + 1的预分频器（41）。 第一信号（MC）被输入到数模转换器（100），使得从数模转换器（100）输出的信号（Idac）与第一信号（MC）对准。 锁相环包括耦合到数模转换器（100）和预分频器（41）的电路（90），以使来自数模转换器（100）的输出中的信号（Idac）与 输出（Prout）从预分频器（41）。