公开(公告)号：EP1424773B1

公开(公告)日：2007-01-24

申请号：EP02425734.7

申请日：2002-11-28

Applicant: STMicroelectronics S.r.l.

Inventor： Radice, Francesco ,  Bruccoleri, Melchiorre

IPC: H03H11/04 ,  H03H11/48

CPC classification number: H03H11/0405 ,  H03H11/481

公开(公告)号：EP1424773A1

公开(公告)日：2004-06-02

申请号：EP02425734.7

申请日：2002-11-28

Applicant: STMicroelectronics S.r.l.

Inventor： Radice, Francesco ,  Bruccoleri, Melchiorre

IPC: H03H11/04 ,  H03H11/48

CPC classification number: H03H11/0405 ,  H03H11/481

Abstract: The invention relates to a circuit device (1) for realising a non-linear reactive elements scale network, wherein the non-linear elements of the network are pairs of inductive (L) and capacitive (C) components cascade connected between a pair of input terminals and a pair of output terminals. Advantageously in the invention, each component (L,C) of the network is formed by cascade connecting a first (2) and a second (3) transconductance (Gm1,Gm2) integrator with each other.

Abstract translation: 本发明涉及一种用于实现非线性无功元素规模网络的电路设备（1），其中网络的非线性元件是级联的电感（L）和电容（C）组件之间的对，所述电感（L）和电容（C） 端子和一对输出端子。 在本发明中有利的是，通过将第一（2）和第二（3）跨导（Gm1，Gm2）积分器彼此级联连接来形成网络的每个部件（L，C）。

公开(公告)号：EP1693965A1

公开(公告)日：2006-08-23

申请号：EP05101333.2

申请日：2005-02-22

Applicant: STMicroelectronics S.r.l.

Inventor： Tonietto, Riccardo ,  Radice, Francesco

IPC: H03K23/42 ,  H03K23/54 ,  H03L7/183 ,  H03L7/099

CPC classification number: H03L7/183 ,  H03L7/0995

Abstract: A frequency divider circuit (108) for obtaining, from a plurality of first signals (ck0,ck60,ck120,ck180,ck240,ck300) having a first frequency (Fo) and being out-of-phase to each other, at least one second signal (Vd) having a second frequency (Fd) equal to a fraction of the first frequency. The frequency divider circuit includes a delaying block (F1,F2,F3) for each first signal, the delaying blocks being series-connected in a closed loop and having a signal input (D1,*D1; D2,*D2; D3,*D3), a signal output (Q1,*Q1; Q2,*Q2; Q3,*Q3) connected to the signal input of a next delaying block in the closed loop, and a clock input (C1,*C1; C2,*C2; C3,*C3) for receiving the corresponding first signal. Each second signal is taken from the signal output of a corresponding delaying block.

Abstract translation: 一种分频器电路，用于从具有第一频率（Fo）并且彼此异相的多个第一信号（ck0，ck60，ck120，ck180，ck240，ck300）获得至少一个 第二信号（Vd）具有等于第一频率的分数的第二频率（Fd）。 分频器电路包括用于每个第一信号的延迟块（F1，F2，F3），延迟块在闭环中串联连接并具有信号输入（D1，* D1; D2，* D2; D3，* D3），连接到闭环中的下一个延迟块的信号输入的信号输出（Q1，* Q1; Q2，* Q2; Q3，* Q3）和时钟输入（C1，* C1; C2，* C2; C3，* C3），用于接收对应的第一信号。 每个第二信号取自相应延迟块的信号输出。