公开(公告)号：US20020025631A1

公开(公告)日：2002-02-28

申请号：US09900501

申请日：2001-07-06

Applicant: STMicroelectronics S.r.l.

Inventor： Roberto Bez ,  Emilio Camerlenghi ,  Stefano Ratti

IPC: H01L021/336

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: A process for fabricating non-volatile memory cells on a semiconductor substrate includes forming a stack structure comprised of a first polysilicon layer isolated from the substrate by an oxide layer. The first polysilicon layer, oxide layer, and semiconductor substrate are cascade etched to define a first portion of a floating gate region of the cell and at least one trench bordering an active area of the memory cell. The at least one trench is filled with an isolation layer. The process further includes depositing a second polysilicon layer onto the whole exposed surface of the semiconductor, and etching the second polysilicon layer to expose the floating gate region formed in the first polysilicon layer, thereby forming extensions adjacent the above portion of the first polysilicon layer.

Abstract translation: 用于在半导体衬底上制造非易失性存储单元的工艺包括由氧化物层形成由与衬底隔离的第一多晶硅层组成的堆叠结构。 级联蚀刻第一多晶硅层，氧化物层和半导体衬底以限定电池的浮动栅极区域的第一部分和与存储器单元的有效区域接合的至少一个沟槽。 至少一个沟槽填充有隔离层。 该方法还包括在半导体的整个暴露表面上沉积第二多晶硅层，以及蚀刻第二多晶硅层以暴露形成在第一多晶硅层中的浮栅区域，从而形成与第一多晶硅层的上述部分相邻的延伸。

公开(公告)号：US20030096477A1

公开(公告)日：2003-05-22

申请号：US10337556

申请日：2003-01-07

Applicant: STMicroelectronics S.r.l.

Inventor： Roberto Bez ,  Emilio Camerlenghi ,  Stefano Ratti

IPC: H01L021/336

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: A process for fabricating non-volatile memory cells on a semiconductor substrate includes forming a stack structure comprised of a first polysilicon layer isolated from the substrate by an oxide layer. The first polysilicon layer, oxide layer, and semiconductor substrate are cascade etched to define a first portion of a floating gate region of the cell and at least one trench bordering an active area of the memory cell. The at least one trench is filled with an isolation layer. The process further includes depositing a second polysilicon layer onto the whole exposed surface of the semiconductor, and etching the second polysilicon layer to expose the floating gate region formed in the first polysilicon layer, thereby forming extensions adjacent the above portion of the first polysilicon layer.