Abstract:
The invention relates to a control circuit (21) of a current sharing bus (CSB) integrated in signal regulator modules, particularly voltage regulator modules (VRM), the circuit (21) being of the Average Program (AP) type. Advantageously, according to the invention, the circuit (21) comprises a voltage regulator module (VRMi), comprising an operational transductance amplifier (OTAi); a first current generator (Gi1), connected to a first input terminal (Pi) of the operational transconductance amplifier (OTAi); a second current generator (Gi2) connected to a second input (Ni) of the operational transconductance amplifier (OTAi). The operational transconductance amplifier (OTAi) is directly driven by currents Ii generated by the first current generator Gi1 and second current generator Gi2.
Abstract:
A method is described for controlling a converter of the multiphase interleaving type comprising the steps of: - detecting when a change of the load applied to an output terminal of the converter occurs; - simultaneously turning off all the phases of the converter; and - recovering a driving interleaving phase shift for restarting a normal operation of the converter. A controller is also described for carrying out this method.
Abstract:
A method is described for controlling a converter of the multiphase interleaving type comprising the steps of: - detecting when a change of the load applied to an output terminal of the converter occurs; - simultaneously turning on all the phases of the converter; and - recovering a driving interleaving phase shift to restart a normal operation of the converter. A controller for carrying out this method is also described.
Abstract:
The invention relates a controller for DC-DC converters (4) with bypass compensation for applications stand alone or multi-phase mode, of the type associated with a half-bridge driving stage (7) of at least one inductive load (2) wherein a pair of power MOS transistors in Highside and Lowside configuration are driven in switching by means of a corresponding converter, the controller having an input connected to a terminal (A) of the inductive load and comprising: a read block (6) of the phase current (Ic) of the inductive load (2) connected to the terminal (A); an over current comparator (8) having an input connected to the output of the read block (6); a bypass compensation network (11) incorporating an error amplifier block (5) having an input coupled to the terminal (A) by means of a voltage divider (3) and a second input coupled to a reference potential (Rref); the compensation network having an output connected to a second input of the over current comparator (8) whose output is applied to the DC-DC converter (4).
Abstract:
A method is described fur- controlling a converter of the multiphase interleaving type comprising the steps of: - detecting when a change of the load applied to an output terminal of the converter occurs by detecting the derivative of a voltage signal of the output terminal; - simultaneously driving all the phases of said converter by zeroing a driving interleaving phase shift on the basis of said detected load transient; and - recovering said driving interleaving phase shift for restarting a normal operation of said converter. A controller is also described for carrying out this method.
Abstract:
A method of controlling a DC-DC converter having means for comparing the output voltage with a low threshold and a high threshold, means injecting a certain minimum electric charge into an inductor of the converter during a conduction phase of at least a power switch, comprises commanding the beginning of a conduction phase each time the output voltage drops below the low threshold, progressively increasing the electric charge transferred during a conduction phase by incrementing its duration until the output voltage rises to said high threshold, starting from said low threshold upon executing a single conduction phase, measuring and storing the duration of the time interval between two consecutive conduction phases, comparing the current time interval with the previously detected and stored time interval, decreasing the duration of the next conduction phase to correspond to said minimum electric charge whenever an increment of the time interval between two consecutive conduction phases is detected. A hardware implementation is also described.