公开(公告)号：EP1610343B1

公开(公告)日：2007-12-19

申请号：EP04102942.2

申请日：2004-06-24

Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

Inventor： Zanardi, Stefano ,  Martinozzi, Giulio

IPC: G11C16/10 ,  G11C16/26

CPC classification number: G11C16/26 ,  G11C16/10 ,  G11C2216/14

公开(公告)号：EP1598831B1

公开(公告)日：2007-11-21

申请号：EP04102232.8

申请日：2004-05-20

Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

Inventor： Khouri, Osama ,  Zanardi, Stefano ,  Martinozzi, Giulio

IPC: G11C16/10 ,  G11C16/26

CPC classification number: G11C16/26

公开(公告)号：EP1610343A1

公开(公告)日：2005-12-28

申请号：EP04102942.2

申请日：2004-06-24

Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

Inventor： Zanardi, Stefano ,  Martinozzi, Giulio

IPC: G11C16/10 ,  G11C16/26

CPC classification number: G11C16/26 ,  G11C16/10 ,  G11C2216/14

Abstract: A page buffer ( 130 ) for an electrically programmable memory ( 100 ) including a plurality of memory cells ( 110 ) forming a plurality of memory pages, the page buffer comprising a plurality of storage units ( 205 ) for at least temporarily storing data read from or to be written into the memory cells of selected memory pages of said plurality, each storage unit comprising a first latch ( 230-1 ) and a second latch ( 230-2 ), operatively associated with a selected bit line ( BLe,BLo ) of memory cells, for reading/programming the data bit from/into a selected memory cell belonging to said bit line, and with a respective data line ( I/O-LINE ), for transporting the data bit read from a selected memory cell to an output interface ( 140,I/O ) of the memory, in which each of said first and second latches in the storage unit includes: a first input/output terminal ( 237-1a,237-2a ) and a second input/output terminal ( 237-1b,237-2b ); input switching means ( 280-1a,280-1b,280-2a,280-2b ) for loading into the latch the data bit to be written and to be temporarily stored in response to an input control signal ( DI-1,DI-2 ) corresponding to the data bit, the input switching means having an input terminal connected to the respective data line for receiving a set voltage provided therethrough, a first output terminal coupled to the first input/output terminal of the latch and a second output terminal coupled to the second input/output terminal, and a control terminal receiving the input control signal, the input switching means providing the set voltage to the first or second input/output terminal of the latch depending on the data bit to be written; and an output switch device ( 280-1b,280-2b ) for transferring onto the respective data line the read data bit temporarily stored into the latch in response to an output control signal ( DO-1,DO-2 ), the output switch device having a first terminal coupled to one among the first and second input/output terminals of the latch, a second terminal connected to the respective data line and a control terminal receiving the output control signal.

Abstract translation: 一种用于电可编程存储器（100）的页缓冲器（130），包括形成多个存储器页的多个存储器单元（110），所述页缓冲器包括多个存储单元（205），用于至少临时存储从 或被写入所述多个选定存储器页的存储单元中，每个存储单元包括与所选位线（BLe，BLo）可操作地相关联的第一锁存器（230-1）和第二锁存器（230-2） 的存储单元，用于从属于所述位线的所选择的存储单元中的数据位读取/编程数据位，以及相应的数据线（I / O-LINE），用于将从选择的存储单元读取的数据位传送到 存储器的输出接口（140，I / O），其中存储单元中的每个所述第一和第二锁存器包括：第一输入/输出端子（237-1a，237-2a）和第二输入/输出 端子（237-1b，237-2b）; 输入切换装置（280-1a，280-1b，280-2a，280-2b），用于响应于输入控制信号（DI-1，DI-1）将要写入的数据位加载到锁存器中并临时存储， 2），输入切换装置具有连接到相应数据线的输入端，用于接收通过其提供的设定电压，耦合到锁存器的第一输入/输出端的第一输出端和第二输出端 耦合到所述第二输入/输出端子，以及控制端子，接收所述输入控制信号，所述输入开关装置根据要写入的数据位向所述锁存器的所述第一或第二输入/输出端提供所述设定电压; 以及用于响应于输出控制信号（DO-1，DO-2）将临时存储到锁存器中的读取数据位传送到相应数据线的输出开关装置（280-1b，280-2b），输出开关 装置，其具有耦合到锁存器的第一和第二输入/输出端子中的一个的第一端子，连接到相应数据线的第二端子和接收输出控制信号的控制端子。

公开(公告)号：EP1598831A1

公开(公告)日：2005-11-23

申请号：EP04102232.8

申请日：2004-05-20

Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

Inventor： Khouri, Osama ,  Zanardi, Stefano ,  Martinozzi, Giulio

IPC: G11C16/10 ,  G11C16/26

CPC classification number: G11C16/26

Abstract: A page buffer ( 130 ) for an electrically programmable memory including a plurality of memory cells ( 110 ) forming a plurality of memory pages, the page buffer comprising at least one register ( 130m,130c ) for at least temporarily storing data read from or to be written into the memory cells of a selected memory page of said plurality, the at least one register comprising a plurality of latches ( 230m ), each latch being operatively associated with at least one respective signal line ( BLe,BLo,I/O-LINE ) transporting the data bit temporarily stored in the latch. A buffer element ( BUF ) is provided for decoupling an output of the latch from the respective signal line, the latch using the respective buffer element for driving the signal line according to the data bit stored therein.

Abstract translation: 一种用于电可编程存储器的页缓冲器（130），所述电可编程存储器包括形成多个存储器页的多个存储器单元（110），所述页缓冲器包括至少一个寄存器（130m，130c），用于至少暂时存储从或者到 被写入所述多个选定存储页中的存储单元，所述至少一个寄存器包括多个锁存器（230m），每个锁存器与至少一个相应信号线（BLe，BLo，I / O- LINE）传输临时存储在锁存器中的数据位。 提供缓冲器元件（BUF），用于将锁存器的输出与相应的信号线去耦，锁存器使用相应的缓冲器元件根据存储在其中的数据位来驱动信号线。