公开(公告)号：EP1184962A1

公开(公告)日：2002-03-06

申请号：EP00830586.4

申请日：2000-08-22

Applicant: STMicroelectronics S.r.l. ,  TECDIS S.p.A.

Inventor： Gariboldi, Roberto ,  Lavorerio, Riccardo ,  Sala, Leonardo ,  Nidasio, Giovanni

IPC: H02M3/07

CPC classification number: H02M3/073

Abstract: This invention relates to a high-efficiency electronic circuit (1) for generating and regulating a supply voltage (Vout), comprising a charge-pump voltage multiplier (2) which is associated with an oscillator (3) and has an output connected to a voltage regulator (4) in order to ultimately output said supply voltage (Vout). Advantageously, the circuit comprises a first hysteresis comparator (5) having as inputs the regulator (4) output and the multiplier (2) output, and comprises a second hysteresis comparator (6) having as inputs a reference potential (Vrif) and a partition (K) of the voltage (Vout) presented on the regulator (4) output.
The comparators are structurally and functionally independent of each other, and their outputs are coupled to the oscillator (3) through a logic circuit (7) to modulate the oscillator (3) operation.

Abstract translation: 本发明涉及一种用于产生和调节的供给电压（Vout），其包括一个电荷泵电压倍增器的高效率电子电路（1）（2）所有其与在振荡器相关联的（3），并且具有对连接到输出 为了电压调节器（4），以最终所述输出电源电压（Vout）。 有利的是，该电路包括一个第一磁滞比较器（5），其具有作为输入的调节器（4）输出和乘法器（2）输出，和包括第二迟滞比较器（6），其具有作为输入的基准电势（Vrif）和分区 的电压的（K）（VOUT）呈现在调节器（4）输出。 比较器在结构上和功能上独立的海誓山盟，并且它们的输出通过一个逻辑电路（7）来调制所述振荡器（3）操作耦合到所述振荡器（3）。

公开(公告)号：EP1184962B1

公开(公告)日：2006-05-17

申请号：EP00830586.4

申请日：2000-08-22

Applicant: STMicroelectronics S.r.l. ,  TECDIS S.p.A.

Inventor： Gariboldi, Roberto ,  Lavorerio, Riccardo ,  Sala, Leonardo ,  Nidasio, Giovanni

IPC: H02M3/07 ,  G05F1/563

CPC classification number: H02M3/073

公开(公告)号：EP1182637A1

公开(公告)日：2002-02-27

申请号：EP00830587.2

申请日：2000-08-22

Applicant: STMicroelectronics S.r.l. ,  TECDIS S.p.A.

Inventor： Gariboldi, Roberto ,  Lavorerio, Riccardo ,  Sala, Leonardo ,  Nidasio, Giovanni

IPC: G09G3/36 ,  G09G5/36

CPC classification number: G09G5/395 ,  G09G3/3611 ,  G09G3/3674 ,  G09G3/3685 ,  G09G2310/0278 ,  G09G2360/02 ,  G09G2360/12

Abstract: Presented is a new memory controller for use in a display, such as a liquid crystal display of the type comprising a set of first drivers (24), and a set of second drivers (26), a portion of which can be converted to said first drivers (26b). Also included is a RAM memory (62) structured to accept data at an input and output said data to the sets of first (24) and second (26) drivers when a master clock signal is received at said RAM memory (62). The memory controller includes a clock signal generator structured to generate said master clock signal; and a control signal generator circuit structured to generate control signals for said RAM memory (62) and said sets of first (24) and second (26) drivers. An important advantage to this memory controller is that it includes a set of auxiliary registers (52) structured to temporarily store a first portion of said data received from said RAM memory (62) after receiving a slave clock cycle, and said set of auxiliary registers (52) structured to output said first portion of data into said portion of said second drivers converted to said first drivers (26b) after receiving said master clock signal. A method is also disclosed that uses the above structure in order to perform the steps of using a folded memory as a way to increase the utilization rate of memory within the display controller.

Abstract translation: 提出了一种用于显示器的新的存储器控​​制器，例如包括一组第一驱动器（24）的类型的液晶显示器和一组第二驱动器（26），其一部分可以转换为所述 第一个司机（26b）。 还包括RAM存储器（62），其被构造为当在所述RAM存储器（62）处接收到主时钟信号时，在输入端接收数据并将所述数据输出到第一（24）和第二（26）驱动器的组。 存储器控制器包括被构造为产生所述主时钟信号的时钟信号发生器; 以及控制信号发生器电路，其被构造为产生用于所述RAM存储器（62）和所述第一（24）和第二（26）驱动器组的控制信号。 该存储器控制器的一个重要优点是它包括一组辅助寄存器（52），其被构造为在接收到从时钟周期之后临时存储从所述RAM存储器（62）接收到的所述数据的第一部分，并且所述一组辅助寄存器 （52），其被构造为在接收到所述主时钟信号之后将所述第一数据部分输出到所述转换成所述第一驱动器（26b）的所述第二驱动器的所述部分。 还公开了一种使用上述结构以便执行使用折叠存储器作为增加显示控制器内的存储器的利用率的方式的方法。