公开(公告)号：EP1032035B1

公开(公告)日：2004-10-13

申请号：EP99830100.6

申请日：1999-02-26

Applicant: STMicroelectronics S.r.l. ,  Wafer Scale Integration, Inc.

Inventor： Pozzoni, Pierantonio ,  Brambilla, Claudio ,  Cereda, Manlio Sergio ,  Caprara, Paolo ,  Irani, Ruston

IPC: H01L21/8247

CPC classification number: H01L27/11521

公开(公告)号：EP1032035A1

公开(公告)日：2000-08-30

申请号：EP99830100.6

申请日：1999-02-26

Applicant: STMicroelectronics S.r.l. ,  Wafer Scale Integration, Inc.

Inventor： Pozzoni, Pierantonio ,  Brambilla, Claudio ,  Cereda, Manlio Sergio ,  Caprara, Paolo ,  Irani, Ruston

IPC: H01L21/8247

CPC classification number: H01L27/11521

Abstract: A process for manufacturing electronic semiconductor integrated electronic memory devices having virtual ground and comprising at least a matrix of floating gate memory cells (1), the matrix being formed on a semiconductor substrate (2) with a plurality of continuous bit lines (10) extending across the substrate (2) as discrete parallel strips, comprising at least the following steps:

forming an oxide layer (3) over the matrix region;
depositing the semiconductor throughout with a stack structure which comprises a first conductor layer (4), first dielectric layer (5), and second conductor layer (6);
forming a second dielectric layer (7);
defining floating gate regions (13) by photolithography using a mask of "POLY1 along a first predetermined direction", and associated etching, to define, in said stack structure, a plurality of parallel openings (9);
implanting said parallel openings (9) to confer a predetermined conductivity on the bit line (10) regions;
filling the parallel openings (12) with a photo-sensitive material (11) to protect the matrix bit lines (10).

Abstract translation: 一种用于制造具有虚地电子半导体集成电子存储器设备和包括至少浮动栅极存储器单元的一个矩阵处理（1）中，基体被连续位线的延伸的多个（10）形成在半导体衬底（2） 横跨基片（2）作为离散的平行条带，其包括至少以下步骤：在所述矩阵区域氧化物层（3）上; 沉积半导体整个具有堆叠结构，其包括第一导体层（4），第一电介质层（5）和第二导体层（6）; 形成第二电介质层（7）; 使用的“沿第一预定方向POLY1”掩模，和相关联的蚀刻， - 定义浮置栅极区域（13），通过光刻，以限定在所述堆叠结构，平行的开口（9）的多元性; 注入所述平行的开口（9），以赋予对位线（10）的区域的预定导电性; 填充开口（12）在平行（11）光敏材料，以保护基质的位线（10）。