公开(公告)号：EP2194646B1

公开(公告)日：2013-01-02

申请号：EP09177501.5

申请日：2009-11-30

Applicant: STMicroelectronics Srl

Inventor： Weltin-Wu, Colin ,  Temporiti Milani, Enrico Stefano ,  Baldi, Daniele

IPC: H03L7/099

CPC classification number: H03L7/0991 ,  H03L2207/50

公开(公告)号：EP2194646A1

公开(公告)日：2010-06-09

申请号：EP09177501.5

申请日：2009-11-30

Applicant: STMicroelectronics Srl

Inventor： Weltin-Wu, Colin ,  Temporiti Milani, Enrico Stefano ,  Baldi, Daniele

IPC: H03L7/099

CPC classification number: H03L7/0991 ,  H03L2207/50

Abstract: A method of improving noise characteristics of an all-digital phase locked loop generating a feedback word representing a continuous-time oscillating signal, including a time-to-digital converter input with the continuous-time oscillating signal and a reference signal function of a reference clock, the time-to-digital converter generating a digital word representing either the ratio between the oscillating signal and the reference signal or the DCO output phase, the feedback word being a function of said digital word, comprises the step of corrupting with a dither signal at least one among the reference clock, the digital word and the oscillating signal.
This method is implemented by a respective feedback circuit for an all-digital phase locked loop.

Abstract translation: 改进的全数字相位的噪声特性的方法，锁相环产生表示连续时间振荡信号的反馈字，包括与连续时间振荡信号的时间 - 数字转换器的输入和基准的基准信号的功能 时钟，时间 - 数字转换器产生代表无论振荡信号和所述基准信号或所述DCO输出相之间的比例的数字字，所述反馈字是所述数字字的一个功能，包括腐败与抖动的步骤 信号的基准时钟，数字字和所述振荡信号中的至少一个。 此方法由一个respectivement反馈电路来实现用于全数字锁相环。