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    System for performing the test of digital circuits
    3.
    发明公开
    System for performing the test of digital circuits 有权
    系统zurdurchfürungeinerPrüfungvon digitalen Schaltkreisen

    公开(公告)号：EP2381265A1

    公开(公告)日：2011-10-26

    申请号：EP11159524.5

    申请日：2011-03-24

    Applicant: STMicroelectronics Srl

    Inventor： Casarsa, Marco

    IPC: G01R31/317

    CPC classification number: G01R31/31724 ,  G01R31/31701 ,  G01R31/318555

    Abstract: It is described a system (1) for performing the test of a digital circuit (2). The system comprises a controller (3) configured for executing the test of the digital circuit, comprises a memory (14) configured for storing a status value of the digital circuit, comprises a state machine (6) configured for controlling, before the execution of the test, the storage into the memory of the status value of the digital circuit and configured for controlling, after the execution of the test, the restore into the digital circuit of the status value stored into the memory.

    Abstract translation: 描述了用于执行数字电路（2）的测试的系统（1）。 该系统包括被配置为执行数字电路的测试的控制器（3），包括被配置为存储数字电路的状态值的存储器（14），包括状态机（6），其被配置为在执行 测试中，存储到存储器中的数字电路的状态值并配置为进行控制，执行测试后，将数字电路的状态值还原存储到存储器中。

    Electrical interconnection integrated device with fault detecting module and electronic apparatus comprising the device
    4.
    发明公开
    Electrical interconnection integrated device with fault detecting module and electronic apparatus comprising the device 有权
    用于与错误检测模块和电子设备的电气连接的集成装置，包括该装置

    公开(公告)号：EP2362233A1

    公开(公告)日：2011-08-31

    申请号：EP11152184.5

    申请日：2011-01-26

    Applicant: STMicroelectronics Srl

    Inventor： Casarsa, Marco

    IPC: G01R31/317

    CPC classification number: G01R31/31715

    Abstract: An electrical interconnection integrated device is described, comprising:
    a plurality of electrical terminals (16-26) connectable to an integrated electronic circuit (400) on a chip common to said interconnection device;
    at least an inside electrical device (43;33;34) provided with a respective input connected to a first terminal (18;24;25) of said plurality and a respective output (57;62;63);
    a fault detecting logic module (50) having a first input (57;62;63) connected to said output of the inner electrical device (43;33;34) and provided with a detecting terminal for supplying a fault detecting signal (ipp_xor).

    Abstract translation: 电互连集成装置被描述，包括：电端子（16-26）连接到在与所述互连装置共同在一个芯片上集成的电子电路（400）的多元性; 至少到内部的电气设备（43; 34; 33），所述多个和respectivement输出设置有连接到第一端子的输入respectivement（25 18; 24）（57; 62; 63）; 连接到内部电设备的所述输出的故障检测逻辑模块（50），具有第一输入端（63 57; 62）（43; 33; 34）和用于供给故障检测信号设置有检测端子（ipp_xor） ，

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