公开(公告)号：EP1851804B1

公开(公告)日：2010-08-04

申请号：EP06723076.3

申请日：2006-02-22

Applicant: STMicroelectronics Srl

Inventor： SAGGIO, Mario, Giuseppe ,  FRISINA, Ferruccio

IPC: H01L29/78 ,  H01L29/36 ,  H01L29/10 ,  H01L29/08 ,  H01L21/336

CPC classification number: H01L29/66712 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/1095

Abstract: Power semiconductor device (30) integrated on a semiconductor substrate (100) of a first type of conductivity comprising a plurality of elemental units, each elemental unit comprising a body region (40) of a second type of conductivity realised on a semiconductor layer (20) of the first type of conductivity formed on the semiconductor substrate (100), and a column region (50) of the first type of conductivity realised in said semiconductor layer (20) below the body region (40), wherein the semiconductor layer (20) comprises a plurality of semiconductor layers (21, 22, 23, 24), overlying each other, the resistivity of each layer being different from that of the other layers, and wherein said column region (50) comprises a plurality of doped sub-regions (51, 52, 53, 54), each realised in one of said semiconductor layers (21, 22, 23, 24), wherein the amount of charge of each doped sub-regions (51, 52, 53, 54) balances the amount of charge of the semiconductor layer (21, 22, 23, 24).

公开(公告)号：EP1908101B1

公开(公告)日：2012-12-26

申请号：EP06762481.7

申请日：2006-07-07

Applicant: STMicroelectronics Srl

Inventor： SAGGIO, Mario, Giuseppe ,  FRISINA, Ferruccio ,  RASCUNA, Simone

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7802 ,  H01L29/0634 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/66712

Abstract: Process for manufacturing a multi-drain power electronic device (30) integrated on a semiconductor substrate (100) of a first type of conductivity, comprising the following steps: forming a first semiconductor layer (21) of the first type of conductivity and of a first resistivity (Á 1 ) value on the semiconductor substrate (100), forming at least a second semiconductor layer (22) of a second type of conductivity of a second resistivity (Á 2 ) value on the first semiconductor layer (21), forming, in this at least a second semiconductor layer (22), a first plurality of implanted regions (D1) of the first type of conductivity by means of a first selective implant step with a first implant dose (¦ 1 ) , forming, above this at least a second semiconductor layer (22), a superficial semiconductor layer (26) of the first type of conductivity of a third resistivity (Á 6 ) value, forming in the surface semiconductor layer (26) body regions (40) of the second type of conductivity, the body regions (40) being aligned with portions of the semiconductor layer (22) free from the plurality of implanted regions (D1), carrying out a thermal diffusion step so that the plurality of implanted regions (D1) form a plurality of electrically continuous implanted column regions (D) along this at least a second semiconductor layer (22), the plurality of column implanted regions (D) delimiting a plurality of column regions (50) of the second type of conductivity aligned with the body regions (40).