公开(公告)号：EP2466451A1

公开(公告)日：2012-06-20

申请号：EP11192081.5

申请日：2011-12-06

Applicant: STMicroelectronics Srl

Inventor： Dondini, Mirko ,  Nastasi, Cristina

IPC: G06F5/08

CPC classification number: G06F5/08

Abstract: Operation of a memory with a plurality of locations (101, 102, 103), such as a FIFO buffer memory envisages:
- writing the data (D1, D2) at input to the memory in a single write location (101); and
- making the single write location (101) available for writing an input datum (D1, D2) with a shift of the datum written in the single write location (101) to another location (102) of the memory.
At each operation of writing of an input datum (D1, D2) in the single write location (101), there is scheduled shifting of the datum written therein to another location (102), without waiting for a new write request, thus eliminating the combinational constraint between the two operations.

Abstract translation: 具有诸如FIFO缓冲存储器的多个位置（101,102,103）的存储器的操作设想： - 在单个写入位置（101）中将数据（D1，D2）输入到存储器中; 以及 - 使所述单个写入位置（101）可用于以写入所述单个写入位置（101）的所述基准的移位写入所述存储器的另一位置（102）来写入输入数据（D1，D2）。 在单个写入位置（101）中对输入数据（D1，D2）进行写入的每个操作时，在其中写入的数据被调度到另一个位置（102），而不需要等待新的写入请求，从而消除 两个操作之间的组合约束。