Abstract:
The proposed phase-change memory cell comprises a substrate (2) housing a selection transistor, an electrical insulation layer (10) having a conductive through via (11a) electrically coupled to a first electrode (4) of the transistor, a heater element (34) including a first portion in electrical contact with the conductive through via and a second portion that extends orthogonal to the first portion, a first protection element (32) extending on the first and second portions of the heater element, a second protection element (40) extending in direct lateral contact with the first portion of the heater element and with the first protection element, and a phase-change region (50) extending over the heater element in electrical and thermal contact therewith.