公开(公告)号：EP2299481A3

公开(公告)日：2011-05-18

申请号：EP10015719.7

申请日：2006-07-07

Applicant: STMicroelectronics Srl

Inventor： Saggio, Mario Giuseppe ,  Frisina, Ferruccio ,  Rascuna, Simone

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7802 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66712

Abstract: Process for manufacturing a multi-drain power electronic device (30) integrated on a semiconductor substrate (100) of a first type of conductivity whereon a drain semiconductor layer (20) is formed, characterised in that it comprises the following steps:
- forming at least a first semiconductor epitaxial layer (21) of the first type of conductivity of a first value of resistivity (ρ 1 ) forming the drain epitaxial layer (20) on the semiconductor substrate (100),
- forming in the first semiconductor layer (21) first sub-regions (51) of a second type of conductivity by means of a first selective implant step with a first implant dose (Φ 1P ),
- forming in the first semiconductor layer (21) second sub-regions (D1, D1a) of the first type of conductivity by means of a second implant step with a second implant dose (Φ 1N ),
- forming a surface semiconductor layer (23) wherein body regions (40) of the second type of conductivity are formed being aligned with the first sub-regions (51),
- carrying out a thermal diffusion process so that the first sub-regions (51) form a single electrically continuous column region (50) being aligned and in electric contact with the body regions (40).