公开(公告)号：EP2466629A3

公开(公告)日：2013-11-27

申请号：EP11193548.2

申请日：2011-12-14

Applicant: STMicroelectronics Srl

Inventor： Borzi, Anna ,  Coccorese, Corrado ,  Morale, Giuseppe ,  Repici, Domenico

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/40

CPC classification number: H01L29/4236 ,  H01L21/31658 ,  H01L21/32105 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

Abstract: A method of forming an MIS (metal-insulator-semiconductor) structure, the method comprising: forming a first semiconductor electrode in a cavity formed in a crystalline semiconductor region by depositing a first silicon containing layer provided with an increased oxidation rate relatively to an exposed surface of said crystalline semiconductor region in said cavity and depositing a second silicon containing layer above said silicon containing layer with a different oxidation rate relatively to said silicon containing layer, said first semiconductor electrode being electrically insulated from said crystalline semiconductor region by an insulating layer, concurrently oxidizing said exposed surface of said crystalline semiconductor region in said cavity and an exposed surface of said first semiconductor electrode so as to form a first oxide layer on said exposed surface of said first semiconductor electrode and a second oxide layer on said exposed surface of said crystalline semiconductor region and forming a second semiconductor electrode in said cavity and above said first semiconductor electrode, said second semiconductor electrode being electrically isolated from said first semiconductor electrode by said first oxide layer.

Abstract translation: 形成设置有增加的氧化的速率在通过沉积第一含硅层在结晶半导体区域中形成的空腔的第一半导体电极相对于在暴露：在MIS（金属 - 绝缘体 - 半导体）结构，该方法包括形成的方法 在所述空腔中所述结晶半导体区域的表面和沉积第二硅含以上所述硅氧烷具有不同的氧化速率相对于所述含硅氧烷层含有层层，所述第一半导体电极电从所述结晶半导体区域由在绝缘层绝缘， 在所述空腔中，并在上述第1半导体电极的暴露的表面同时氧化所述结晶半导体区域的所述暴露表面，从而形成一第一氧化物层在所述暴露在所述第一半导体电极上和所述第二氧化物层的表面暴露在所述的表面 结晶性半导体 区和形成在所述空腔中和高于所述第一半导体电极的第二半导体电极，所述第二半导体电极由所述第一氧化物层从所述第一半导体电极电隔离。

公开(公告)号：EP2466629B1

公开(公告)日：2017-10-11

申请号：EP11193548.2

申请日：2011-12-14

Applicant: STMicroelectronics Srl

Inventor： Borzi, Anna ,  Coccorese, Corrado ,  Morale, Giuseppe ,  Repici, Domenico

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/40

CPC classification number: H01L29/4236 ,  H01L21/31658 ,  H01L21/32105 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

Abstract: A method of forming an MIS (metal-insulator-semiconductor) structure, the method comprising: forming a first semiconductor electrode in a cavity formed in a crystalline semiconductor region by depositing a first silicon containing layer provided with an increased oxidation rate relatively to an exposed surface of said crystalline semiconductor region in said cavity and depositing a second silicon containing layer above said silicon containing layer with a different oxidation rate relatively to said silicon containing layer, said first semiconductor electrode being electrically insulated from said crystalline semiconductor region by an insulating layer, concurrently oxidizing said exposed surface of said crystalline semiconductor region in said cavity and an exposed surface of said first semiconductor electrode so as to form a first oxide layer on said exposed surface of said first semiconductor electrode and a second oxide layer on said exposed surface of said crystalline semiconductor region and forming a second semiconductor electrode in said cavity and above said first semiconductor electrode, said second semiconductor electrode being electrically isolated from said first semiconductor electrode by said first oxide layer.

公开(公告)号：EP2466629A2

公开(公告)日：2012-06-20

申请号：EP11193548.2

申请日：2011-12-14

Applicant: STMicroelectronics Srl

Inventor： Borzi, Anna ,  Coccorese, Corrado ,  Morale, Giuseppe ,  Repici, Domenico

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/40

CPC classification number: H01L29/4236 ,  H01L21/31658 ,  H01L21/32105 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

Abstract: A method of forming an MIS (metal-insulator-semiconductor) structure, the method comprising: forming a first semiconductor electrode in a cavity formed in a crystalline semiconductor region by depositing a first silicon containing layer provided with an increased oxidation rate relatively to an exposed surface of said crystalline semiconductor region in said cavity and depositing a second silicon containing layer above said silicon containing layer with a different oxidation rate relatively to said silicon containing layer, said first semiconductor electrode being electrically insulated from said crystalline semiconductor region by an insulating layer, concurrently oxidizing said exposed surface of said crystalline semiconductor region in said cavity and an exposed surface of said first semiconductor electrode so as to form a first oxide layer on said exposed surface of said first semiconductor electrode and a second oxide layer on said exposed surface of said crystalline semiconductor region and forming a second semiconductor electrode in said cavity and above said first semiconductor electrode, said second semiconductor electrode being electrically isolated from said first semiconductor electrode by said first oxide layer.