公开(公告)号：EP2273543A3

公开(公告)日：2011-10-26

申请号：EP10183287.1

申请日：2001-12-14

Applicant: STMicroelectronics Srl

Inventor： Tiziani, Roberto ,  Passagrilli, Carlo

IPC: H01L21/60 ,  H01L23/00

CPC classification number: H01L24/05 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05001 ,  H01L2224/05083 ,  H01L2224/05118 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48824 ,  H01L2224/48844 ,  H01L2224/48855 ,  H01L2224/48864 ,  H01L2224/85205 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12036 ,  H01L2924/14 ,  H01L2924/20755 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015

Abstract: A semiconductor electronic device (1) is disclosed, which comprises a die (2) of semiconductor material and a support (3), the die (2) of semiconductor material including an integrated electronic circuit and a plurality of contact pads (6) associated with the electronic circuit and connected electrically to the support (3) by wire leads (4), each contact pad of said plurality of contact pads (6) comprising a lower layer (7) of copper, or alloys thereof; and an upper layer. Advantageously, the upper layer consists of:
a first film (9) of nickel or alloys thereof, overlying the lower layer (7) of copper or alloys thereof; and
a second film (10) of gold or alloys thereof, overlying the first film (9) of nickel or alloys thereof.
Moreover, the layer (7) or film (9, 10) are deposited by an electroless chemical process.

Abstract translation: 本发明公开了一种半导体电子器件（1），其包括半导体材料管芯（2）和支撑件（3），半导体材料管芯（2）包括集成电子电路和多个关联焊盘（6） 所述多个接触焊盘（6）中的每一个接触焊盘包括铜或其合金的下层（7）;其中所述电子电路通过导线（4）电连接到所述支撑件（3） 和上层。 有利的是，上层由以下部分组成：第一层镍或其合金薄膜（9），覆盖在铜或其合金的下层（7）上; 和覆盖镍或其合金的第一膜（9）的第二层金或其合金薄膜（10）。 此外，通过无电化学处理来沉积层（7）或膜（9,10）。

公开(公告)号：EP2306503A3

公开(公告)日：2011-11-02

申请号：EP10183300.2

申请日：2001-12-14

Applicant: STMicroelectronics Srl

Inventor： Tiziani, Roberto ,  Passagrilli, Carlo

IPC: H01L21/60 ,  H01L23/00

CPC classification number: H01L24/05 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05001 ,  H01L2224/05083 ,  H01L2224/05118 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48824 ,  H01L2224/48844 ,  H01L2224/48855 ,  H01L2224/48864 ,  H01L2224/85205 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12036 ,  H01L2924/14 ,  H01L2924/20755 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015

Abstract: A semiconductor electronic device (1) is disclosed, which comprises a die (2) of semiconductor material and a support (3), the die (2) of semiconductor material including an integrated electronic circuit and a plurality of contact pads (6) associated with the electronic circuit and connected electrically to the support (3) by wire leads (4), characterized in that each contact pad of said plurality of contact pads (6) comprising a lower layer (7) of copper, or alloys thereof; and an upper layer. Advantageously, the upper layer consists of:
a first film (9) of palladium or alloys thereof, overlying the lower layer (7) of copper or alloys thereof; and optionally
a second film (10) of gold or alloys thereof, overlying the first film (9) of palladium or alloys thereof.
Moreover, the layer (7) or film (9, 10) are deposited by an electroless chemical process.

Abstract translation: 本发明公开了一种半导体电子器件（1），其包括半导体材料管芯（2）和支撑件（3），半导体材料管芯（2）包括集成电子电路和多个关联焊盘（6） 与所述电子电路并且通过引线（4）电连接到所述支撑件（3），其特征在于，所述多个接触垫（6）中的每个接触垫包括铜或其合金的下层（7）; 和上层。 有利的是，上层由以下部分组成： - 钯或其合金的第一膜（9），覆盖在铜或其合金的下层（7）上; 以及可选地覆盖钯或其合金的第一膜（9）的第二金（或其合金）膜（10）。 此外，通过无电化学处理来沉积层（7）或膜（9,10）。

公开(公告)号：EP1320129B1

公开(公告)日：2011-07-13

申请号：EP01830768.6

申请日：2001-12-14

Applicant: STMicroelectronics Srl

Inventor： Tiziani, Roberto ,  Passagrilli, Carlo

IPC: H01L21/60

CPC classification number: H01L24/05 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05001 ,  H01L2224/05083 ,  H01L2224/05118 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48824 ,  H01L2224/48844 ,  H01L2224/48855 ,  H01L2224/48864 ,  H01L2224/85205 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12036 ,  H01L2924/14 ,  H01L2924/20755 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015

公开(公告)号：EP2293325B1

公开(公告)日：2013-06-12

申请号：EP10183262.4

申请日：2001-12-14

Applicant: STMicroelectronics Srl

Inventor： Tiziani, Roberto ,  Passagrilli, Carlo

IPC: H01L23/532 ,  H01L23/485 ,  H01L21/60

CPC classification number: H01L24/05 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05001 ,  H01L2224/05083 ,  H01L2224/05118 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48824 ,  H01L2224/48844 ,  H01L2224/48855 ,  H01L2224/48864 ,  H01L2224/85205 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12036 ,  H01L2924/14 ,  H01L2924/20755 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015

公开(公告)号：EP2273544A3

公开(公告)日：2011-10-26

申请号：EP10183317.6

申请日：2001-12-14

Applicant: STMicroelectronics Srl

Inventor： Tiziani, Roberto ,  Passagrilli, Carlo

IPC: H01L21/60 ,  H01L23/00

CPC classification number: H01L24/05 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05001 ,  H01L2224/05083 ,  H01L2224/05118 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48824 ,  H01L2224/48844 ,  H01L2224/48855 ,  H01L2224/48864 ,  H01L2224/85205 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12036 ,  H01L2924/14 ,  H01L2924/20755 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015

Abstract: A semiconductor electronic device (1) is disclosed, which comprises a die (2) of semiconductor material and a support (3), the die (2) of semiconductor material including an integrated electronic circuit and a plurality of contact pads (6) associated with the electronic circuit and connected electrically to the support (3) by wire leads (4), each contact pad of said plurality of contact pads (6) comprising a lower layer (7) of copper, or alloys thereof; and an upper layer. Advantageously, the upper layer consists of:
a first film (9) of nickel or alloys thereof, overlying the lower layer (7) of copper or alloys thereof;
a second film of palladium or alloys thereof, overlying the first film (9) of nickel or alloys thereof; and optionally
a third film (10) of gold or alloys thereof, overlying the second film of palladium or alloys thereof.
Moreover, the layer or film (9, 10) are deposited by an electroless chemical process.

Abstract translation: 本发明公开了一种半导体电子器件（1），其包括半导体材料管芯（2）和支撑件（3），半导体材料管芯（2）包括集成电子电路和多个关联焊盘（6） 所述多个接触焊盘（6）中的每一个接触焊盘包括铜或其合金的下层（7）;其中所述电子电路通过导线（4）电连接到所述支撑件（3） 和上层。 有利的是，上层由以下部分组成：第一层镍或其合金薄膜（9），覆盖在铜或其合金的下层（7）上; 覆盖镍或其合金的第一膜（9）的钯或其合金的第二膜; 以及可选的覆盖钯或其合金的第二膜的第三层金或其合金膜（10）。 此外，通过无电化学处理来沉积层或膜（9,10）。

公开(公告)号：EP2293325A3

公开(公告)日：2011-10-26

申请号：EP10183262.4

申请日：2001-12-14

Applicant: STMicroelectronics Srl

Inventor： Tiziani, Roberto ,  Passagrilli, Carlo

IPC: H01L21/60

CPC classification number: H01L24/05 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05001 ,  H01L2224/05083 ,  H01L2224/05118 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48824 ,  H01L2224/48844 ,  H01L2224/48855 ,  H01L2224/48864 ,  H01L2224/85205 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12036 ,  H01L2924/14 ,  H01L2924/20755 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015

Abstract: A semiconductor electronic device (1) is disclosed, which comprises a die (2) of semiconductor material and a support (3), the die (2) of semiconductor material including an integrated electronic circuit and a plurality of contact pads (6) associated with the electronic circuit and connected electrically to the support (3) by wire leads (4), each contact pad of said plurality of contact pads (6) comprising a lower layer (7) of aluminium, or alloys thereof and an upper layer. Advantageously the upper layer consists of:
a first film (8) of zinc overlying the lower layer (7) of aluminium or alloys thereof;
a second film (9) of nickel or alloys thereof, overlying the first film (8) of zinc;
a third film of palladium or alloys thereof, overlying the second film (9) of nickel or alloys thereof; and optionally
a fourth film (10) of gold or alloys thereof, overlying the third film of palladium or alloys thereof.
Moreover, the layer (7) or film (8,9, 10) are deposited by an electroless chemical process.

Abstract translation: 本发明公开了一种半导体电子器件（1），其包括半导体材料管芯（2）和支撑件（3），半导体材料管芯（2）包括集成电子电路和多个关联焊盘（6） 与电子电路并且通过引线（4）电连接到支撑件（3），所述多个接触垫（6）中的每个接触垫包括铝或其合金的下层（7）和上层。 有利地，上层由以下组成：覆盖在铝或其合金的下层（7）上的锌的第一膜（8） 覆盖锌的第一薄膜（8）的第二薄膜（9）或其合金; 覆盖镍或其合金的第二膜（9）的钯或其合金的第三膜; 以及可选地覆盖钯或其合金的第三膜的第四层金或其合金膜（10）。 此外，通过无电化学处理来沉积层（7）或膜（8,9,10）。

公开(公告)号：EP2273542A3

公开(公告)日：2011-10-26

申请号：EP10183247.5

申请日：2001-12-14

Applicant: STMicroelectronics Srl

Inventor： Tiziani, Roberto ,  Passagrilli, Carlo

IPC: H01L21/60 ,  H01L23/00

CPC classification number: H01L24/05 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05001 ,  H01L2224/05083 ,  H01L2224/05118 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48824 ,  H01L2224/48844 ,  H01L2224/48855 ,  H01L2224/48864 ,  H01L2224/85205 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12036 ,  H01L2924/14 ,  H01L2924/20755 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015

Abstract: A semiconductor electronic device (1) is disclosed, which comprises a die (2) of semiconductor material and a support (3), the die (2) of semiconductor material including an integrated electronic circuit and a plurality of contact pads (6) associated with the electronic circuit and connected electrically to the support (3) by wire leads (4), each contact pad of said plurality of contact pads (6) comprising a lower layer (7) of aluminium or alloys thereof, and an upper layer. Advantageously the upper layer consists of:
a first film (9) of palladium or alloys thereof, overlying the lower layer (7) of aluminium or alloys thereof; and optionally
a second film (10) of gold or alloys thereof, overlying the first film (9) of palladium or alloys thereof.
Moreover, the layer (7) or film (9, 10) are deposited by an electroless chemical process.

Abstract translation: 本发明公开了一种半导体电子器件（1），其包括半导体材料管芯（2）和支撑件（3），半导体材料管芯（2）包括集成电子电路和多个关联焊盘（6） 与电子电路并且通过引线（4）电连接到支撑件（3），所述多个接触垫（6）中的每个接触垫包括铝或其合金的下层（7）以及上层。 有利的是，上层由以下部分组成：钯或其合金的第一膜（9），覆盖铝或其合金的下层（7）; 以及可选地覆盖钯或其合金的第一膜（9）的第二金（或其合金）膜（10）。 此外，通过无电化学处理来沉积层（7）或膜（9,10）。