公开(公告)号：EP1612565B1

公开(公告)日：2011-01-19

申请号：EP05105662.0

申请日：2005-06-24

Applicant: STMicroelectronics Srl ,  STMicroelectronics, Inc.

Inventor： Pasolini, Fabio ,  Tronconi, Michele ,  Lin, Wen ,  Raasch, William

IPC: G01P15/00 ,  G01P15/18 ,  G11B19/04

CPC classification number: G11B19/043 ,  G01P1/127 ,  G01P1/14 ,  G01P15/0891 ,  G01P15/18

Abstract: In an integrated free-fall detection device (16) for a portable apparatus (10), an acceleration sensor (20) generates acceleration signals (A x , A y , A z ) correlated to the components of the acceleration of the portable apparatus along three detection axes (x, y, z). A dedicated purely hardware circuit (24), connected to the acceleration sensor (20), generates in a continuous way and in real-time a free-fall detection signal (F). The free-fall detection signal (F) has a first logic value in the event that the acceleration signals (A x , A y , A z ) are simultaneously lower than a respective acceleration threshold (A th ), and is sent to a processor unit (18) of the portable apparatus (10) as an interrupt signal to activate appropriate actions of protection for the portable apparatus (10). The acceleration sensor (20) and the dedicated purely hardware circuit (24) are integrated in a single chip, and the acceleration sensor (20) is made as a MEMS.

公开(公告)号：EP1288774A2

公开(公告)日：2003-03-05

申请号：EP02255629.4

申请日：2002-08-13

Applicant: STMicroelectronics, Inc.

Inventor： Lin, Wen

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0656 ,  G06F3/0689

Abstract: A computing system having a processor with a data/control bus interface. A data/control bus implements one or more device communication channels. A data memory is coupled to the processor and a mass storage device having an interface for communicating mass storage transactions is provided. A controller having a memory interface is coupled to the data memory and a mass storage interface coupled to the mass storage device's interface and operable to conduct mass storage transactions between the data memory and the mass storage device.

Abstract translation: 具有具有数据/控制总线接口的处理器的计算系统。 数据/控制总线实现一个或多个设备通信信道。 数据存储器耦合到处理器，并且提供了具有用于传送大容量存储器事务的接口的大容量存储设备。 具有存储器接口的控制器耦合到数据存储器和大容量存储接口，大容量存储接口耦合到大容量存储设备的接口并且可操作以在数据存储器和大容量存储设备之间进行海量存储事务。

公开(公告)号：EP1288774A3

公开(公告)日：2007-04-04

申请号：EP02255629.4

申请日：2002-08-13

Applicant: STMicroelectronics, Inc.

Inventor： Lin, Wen

IPC: G06F3/06 ,  G06F13/16

CPC classification number: G06F3/0613 ,  G06F3/0656 ,  G06F3/0689

Abstract: A computing system having a processor with a data/control bus interface. A data/control bus implements one or more device communication channels. A data memory is coupled to the processor and a mass storage device having an interface for communicating mass storage transactions is provided. A controller having a memory interface is coupled to the data memory and a mass storage interface coupled to the mass storage device's interface and operable to conduct mass storage transactions between the data memory and the mass storage device.