公开(公告)号：WO2014205353A3

公开(公告)日：2015-02-19

申请号：PCT/US2014043421

申请日：2014-06-20

Applicant: STRATIO INC

Inventor： LEE JAE HYUNG ,  NA YEUL ,  KIM YOUNGSIK ,  JUNG WOO-SHIK

IPC: H01L27/14 ,  H01L27/142 ,  H01L27/146

CPC classification number: H01L27/14649 ,  H01L27/14614 ,  H01L27/14616 ,  H01L27/14689 ,  H04N5/361

Abstract: A device for sensing light includes a first semiconductor region doped with a dopant of a first type and a second semiconductor region doped with a dopant of a second type. The second semiconductor region is positioned above the first semiconductor region. The device includes a gate insulation layer; a gate, a source, and a drain. The second semiconductor region has a top surface that is positioned toward the gate insulation layer and a bottom surface that is positioned opposite to the top surface of the second semiconductor region. The second semiconductor region has an upper portion that includes the top surface of the second semiconductor region and a lower portion that includes the bottom surface of the second semiconductor region and is mutually exclusive with the upper portion. The first semiconductor region is in contact with both the upper portion and the lower portion of the second semiconductor region.

Abstract translation: 用于感测光的装置包括掺杂有第一类型的掺杂剂的第一半导体区域和掺杂有第二类型的掺杂剂的第二半导体区域。 第二半导体区域位于第一半导体区域的上方。 该器件包括栅极绝缘层; 一个门，一个源头和一个排水沟。 第二半导体区域具有朝向栅极绝缘层定位的顶表面和与第二半导体区域的顶表面相对定位的底表面。 第二半导体区域具有包括第二半导体区域的顶表面的上部和包括第二半导体区域的底表面并且与上部相互排斥的下部。 第一半导体区域与第二半导体区域的上部和下部两者接触。

公开(公告)号：EP3111466A4

公开(公告)日：2017-03-29

申请号：EP16750355

申请日：2016-05-23

Applicant: STRATIO INC

Inventor： LEE JAE HYUNG ,  NA YEUL ,  KIM YOUNGSIK ,  JUNG WOO-SHIK

IPC: H01L21/20 ,  H01L21/308

CPC classification number: H01L21/3081 ,  H01L21/02057 ,  H01L21/02082 ,  H01L21/02636 ,  H01L21/30604

Abstract: A method for removing nuclei formed during a selective epitaxial growth process includes epitaxially growing a first group of one or more semiconductor structures over a substrate with one or more mask layers. A second group of a plurality of semiconductor structures is formed on the one or more mask layers. The method also includes forming one or more protective layers over the first group of one or more semiconductor structures. At least a subset of the second group of the plurality of semiconductor structures is exposed from the one or more protective layers. The method further includes, subsequent to forming the one or more protective layers over the first group of one or more semiconductor structures, etching at least the subset of the second group of the plurality of semiconductor structures.

Abstract translation: 用于去除在选择性外延生长工艺期间形成的核的方法包括在具有一个或多个掩模层的衬底上外延生长第一组一个或多个半导体结构。 在所述一个或多个掩模层上形成第二组多个半导体结构。 该方法还包括在第一组一个或多个半导体结构上形成一个或多个保护层。 第二组多个半导体结构的至少一个子集从一个或多个保护层暴露。 该方法进一步包括，在第一组一个或多个半导体结构上方形成一个或多个保护层之后，蚀刻多个半导体结构的第二组的至少该子集。

公开(公告)号：EP3011594A4

公开(公告)日：2017-03-01

申请号：EP14814462

申请日：2014-06-20

Applicant: STRATIO INC

Inventor： LEE JAE HYUNG ,  NA YEUL ,  KIM YOUNGSIK ,  JUNG WOO-SHIK

IPC: H01L27/146

CPC classification number: H01L27/14649 ,  H01L27/14614 ,  H01L27/14616 ,  H01L27/14689 ,  H04N5/361

Abstract: A device for sensing light includes a first semiconductor region doped with a dopant of a first type and a second semiconductor region doped with a dopant of a second type. The second semiconductor region is positioned above the first semiconductor region. The device includes a gate insulation layer; a gate, a source, and a drain. The second semiconductor region has a top surface that is positioned toward the gate insulation layer and a bottom surface that is positioned opposite to the top surface of the second semiconductor region. The second semiconductor region has an upper portion that includes the top surface of the second semiconductor region and a lower portion that includes the bottom surface of the second semiconductor region and is mutually exclusive with the upper portion. The first semiconductor region is in contact with both the upper portion and the lower portion of the second semiconductor region.