公开(公告)号：WO2013190901A9

公开(公告)日：2014-10-16

申请号：PCT/JP2013061917

申请日：2013-04-23

Applicant: SUMITOMO ELECTRIC INDUSTRIES

Inventor： YAMADA SHUNSUKE ,  TAMASO HIDETO

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/12 ,  H01L29/78

CPC classification number: H01L29/1608 ,  H01L21/0485 ,  H01L21/32053 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/7802 ,  Y10S438/931

Abstract: This silicon carbide semiconductor device (1) comprises a silicon carbide substrate (10) and a contact electrode (16). The silicon carbide substrate (10) includes an n-type region (14) and a p-type region (18) that is in contact with the n-type region (14). The contact electrode (16) is in contact with the n-type region (14) and the p-type region (18). The contact electrode (16) includes Ni atoms and Si atoms. The number of Ni atoms is from 87% to 92%, inclusive, of the total number of Ni atoms and Si atoms. Thus, it is possible to provide a silicon carbide semiconductor device that is capable of making ohmic contact with an n-type impurity region and capable of achieving low contact resistance with respect to a p-type impurity region, and a method for producing said silicon carbide semiconductor device.

Abstract translation: 该碳化硅半导体器件（1）包括碳化硅衬底（10）和接触电极（16）。 碳化硅衬底（10）包括与n型区域（14）接触的n型区域（14）和p型区域（18）。 接触电极（16）与n型区域（14）和p型区域（18）接触。 接触电极（16）包括Ni原子和Si原子。 Ni原子的数量为Ni原子和Si原子总数的87％〜92％。 因此，可以提供能够与n型杂质区域进行欧姆接触并且能够实现相对于p型杂质区域的低接触电阻的碳化硅半导体器件，以及制造所述硅 碳化物半导体器件。

公开(公告)号：WO2011142288A9

公开(公告)日：2012-04-19

申请号：PCT/JP2011060507

申请日：2011-05-02

Applicant: SUMITOMO ELECTRIC INDUSTRIES ,  SHIOMI HIROMU ,  TAMASO HIDETO

Inventor： SHIOMI HIROMU ,  TAMASO HIDETO

IPC: H01L21/02 ,  H01L21/336 ,  H01L29/12 ,  H01L29/47 ,  H01L29/78 ,  H01L29/872

CPC classification number: H01L29/1608 ,  H01L21/02002 ,  H01L21/0495 ,  H01L21/2007 ,  H01L29/0878 ,  H01L29/1066 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/808 ,  H01L29/872

Abstract: Disclosed is a low-cost, high-quality semiconductor device, a bonded substrate used in the manufacture of said semiconductor device, and manufacturing methods therefor. The disclosed method for manufacturing a semiconductor element comprises: a step (S10) in which a single-crystal semiconductor member is prepared; a step (S20) in which a support material is prepared; a step (S30) in which the support material and the single-crystal semiconductor member are bonded to each other using a carbon-containing bonding layer; a step (S40) in which an epitaxial layer is formed on the surface of the single-crystal semiconductor member; a step (S50) in which the epitaxial layer is used to form a semiconductor element; a step (S60), after the step (S50) in which the semiconductor element is formed, in which the bonding layer is broken down via oxidation and the single-crystal semiconductor member is separated from the support material; and a step (S80) in which the single-crystal semiconductor member separated from the support material is diced.

Abstract translation: 公开了一种低成本，高质量的半导体器件，用于制造所述半导体器件的键合衬底及其制造方法。 所公开的半导体元件的制造方法包括：准备单晶半导体部件的工序（S10） 步骤（S20），其中制备支撑材料; 使用含碳接合层将载体材料和单晶半导体部件彼此接合的工序（S30） 在所述单晶半导体部件的表面形成有外延层的工序（S40） 步骤（S50），其中外延层用于形成半导体元件; 步骤（S60），在形成有半导体元件的步骤（S50）之后，通过氧化将接合层分解，并且将单晶半导体部件与支撑材料分离; 以及与支撑材料分离的单晶半导体部件被切割的步骤（S80）。

公开(公告)号：WO2010134415A9

公开(公告)日：2011-08-25

申请号：PCT/JP2010057112

申请日：2010-04-22

Applicant: SUMITOMO ELECTRIC INDUSTRIES ,  WADA KEIJI ,  TAMASO HIDETO ,  MASUDA TAKEYOSHI ,  HONAGA MISAKO

Inventor： WADA KEIJI ,  TAMASO HIDETO ,  MASUDA TAKEYOSHI ,  HONAGA MISAKO

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/337 ,  H01L21/768 ,  H01L29/12 ,  H01L29/417 ,  H01L29/78 ,  H01L29/808

CPC classification number: H01L21/0485 ,  H01L21/0455 ,  H01L29/1608 ,  H01L29/401 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/808

Abstract: Disclosed is a silicon carbide semiconductor device which, when the electrode material is different from the material of the internal interconnects, eliminates the possibility of trouble at the contact interface of these different metals, and has high reliability even after long periods of use. The semiconductor device is provided with contact electrodes (16) which contact silicon carbide (14, 18), and interconnects (19) which connect with the contact electrodes. The contact electrodes (16) are formed from an alloy containing titanium, aluminum, and silicon. The interconnects (19) are formed either from aluminum or aluminum alloy and are connected with the contact electrodes by contacting the contact electrodes.

Abstract translation: 公开了一种碳化硅半导体器件，当电极材料与内部互连的材料不同时，消除了在这些不同金属的接触界面处的麻烦的可能性，并且即使在长时间使用后也具有高可靠性。 半导体器件具有接触碳化硅（14,18）的接触电极（16）和与接触电极连接的互连（19）。 接触电极（16）由含有钛，铝和硅的合金形成。 互连（19）由铝或铝合金形成，并通过接触电极与接触电极连接。

公开(公告)号：WO2012060222A9

公开(公告)日：2012-10-11

申请号：PCT/JP2011073995

申请日：2011-10-19

Applicant: SUMITOMO ELECTRIC INDUSTRIES ,  TAMASO HIDETO

Inventor： TAMASO HIDETO

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/12 ,  H01L29/78

CPC classification number: H01L29/66068 ,  H01L21/0485 ,  H01L21/268 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/7802

Abstract: An electrode layer (16) makes contact with the top of a silicon carbide base substrate (90) and contains Ni atoms and Si atoms. The number of Ni atoms is at least 67% of the total number of Ni atoms and Si atoms. At least the side of the electrode layer (16) making contact with the silicon carbide substrate (90) contains a compound of Si and Ni. At the surface of the electrode layer (16) the concentration of C atoms is less than the concentration of Ni atoms. Thus, the electrical conductivity of the electrode layer (16) can be improved and the precipitation of C atoms on the surface of the electrode layer (16) can be suppressed.

Abstract translation: 电极层（16）与碳化硅基底（90）的顶部接触并且包含Ni原子和Si原子。 Ni原子的数量至少为Ni原子和Si原子总数的67％。 至少与碳化硅衬底（90）接触的电极层（16）的一侧包含Si和Ni的化合物。 在电极层（16）的表面处，C原子的浓度小于Ni原子的浓度。 由此，能够提高电极层（16）的导电性，并且能够抑制电极层（16）表面的C原子的析出。

公开(公告)号：CA2778307A1

公开(公告)日：2011-11-17

申请号：CA2778307

申请日：2011-05-02

Applicant: SUMITOMO ELECTRIC INDUSTRIES

Inventor： SHIOMI HIROMU ,  TAMASO HIDETO

IPC: H01L21/02 ,  H01L21/336 ,  H01L29/12 ,  H01L29/47 ,  H01L29/78 ,  H01L29/872

Abstract: Disclosed is a low-cost, high-quality semiconductor device, a bonded substrate used in the manufacture of said semiconductor device, and manufacturing methods therefor. The disclosed method for manufacturing a semiconductor element comprises: a step (S10) in which a single-crystal semiconductor member is prepared; a step (S20) in which a support material is prepared; a step (S30) in which the support material and the single-crystal semiconductor member are bonded to each other using a carbon-containing bonding layer; a step (S40) in which an epitaxial layer is formed on the surface of the single-crystal semiconductor member; a step (S50) in which the epitaxial layer is used to form a semiconductor element; a step (S60), after the step (S50) in which the semiconductor element is formed, in which the bonding layer is broken down via oxidation and the single-crystal semiconductor member is separated from the support material; and a step (S80) in which the single-crystal semiconductor member separated from the support material is diced.

公开(公告)号：CA2672259A1

公开(公告)日：2008-06-19

申请号：CA2672259

申请日：2007-11-29

Applicant: SUMITOMO ELECTRIC INDUSTRIES

Inventor： TAMASO HIDETO ,  FUJIKAWA KAZUHIRO ,  HARADA SHIN

IPC: H01L21/265 ,  H01L21/28 ,  H01L29/417 ,  H01L29/78

Abstract: A semiconductor device manufacturing method comprising a first step of fo rming an ion implantation mask (103) in a partial region of the surface of a semiconductor (102), a second step of implanting ions of a first dopant int o at least a part of the exposed region of the surface of the semiconductor (102) other than the region where the ion implantation mask (103) is formed and forming a first dopant implantation region (106), a third step of removi ng a part of the ion implantation mask (103) after the formation of the firs t dopant implantation region (106) to enlarge the exposed region of the surf ace of the semiconductor (102), and a fourth step of implanting ions of a se cond dopant into at least a part of the enlarged exposed region of the surfa ce of the semiconductor (102) to form a second dopant implantation region (1 07).

公开(公告)号：CA2762623A1

公开(公告)日：2010-11-25

申请号：CA2762623

申请日：2010-04-22

Applicant: SUMITOMO ELECTRIC INDUSTRIES

Inventor： WADA KEIJI ,  TAMASO HIDETO ,  MASUDA TAKEYOSHI ,  HONAGA MISAKO

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/337 ,  H01L21/768 ,  H01L29/12 ,  H01L29/417 ,  H01L29/78 ,  H01L29/808

Abstract: Disclosed is a silicon carbide semiconductor device which, when the electrode material is different from the material of the internal interconnects, eliminates the possibility of trouble at the contact interface of these different metals, and has high reliability even after long periods of use. The semiconductor device is provided with contact electrodes (16) which contact silicon carbide (14, 18), and interconnects (19) which connect with the contact electrodes. The contact electrodes (16) are formed from an alloy containing titanium, aluminum, and silicon. The interconnects (19) are formed either from aluminum or aluminum alloy and are connected with the contact electrodes by contacting the contact electrodes.

公开(公告)号：CA2667648A1

公开(公告)日：2008-05-08

申请号：CA2667648

申请日：2007-08-13

Applicant: SUMITOMO ELECTRIC INDUSTRIES

Inventor： TAMASO HIDETO ,  FUJIKAWA KAZUHIRO

IPC: H01L21/28

Abstract: Disclosed are: an ohmic electrode (2) for a SiC semiconductor, comprising Si and Ni, or an ohmic electrode (2) for a SiC semiconductor, comprising Si and Ni and additionally comprising Au or Pt; a method for manufacturing the ohmic electrode (2); a semiconductor device using the ohmic electrode (2); and a method for manufacturing the semiconductor device.

公开(公告)号：CA2769697A1

公开(公告)日：2011-10-20

申请号：CA2769697

申请日：2010-04-14

Applicant: SUMITOMO ELECTRIC INDUSTRIES

Inventor： TAMASO HIDETO

IPC: H01L21/28 ,  H01L21/337 ,  H01L29/417 ,  H01L29/78 ,  H01L29/808 ,  H01L29/861

Abstract: Disclosed are: a silicon carbide semiconductor device which comprises an ohmic electrode that has achieved improved adhesion to a wiring line by suppressing deposition of carbon without forming a Schottky contact; and a method for manufacturing the silicon carbide semiconductor device. Specifically, when an ohmic electrode is formed for an SiC semiconductor device, a first metal layer (12) that is formed of a first metal element is formed on one main surface of an SiC layer (11). Meanwhile, an Si layer (13) that is formed of Si is formed on a surface of the first metal layer, said surface being on the reverse side of the surface facing the SiC layer (11). A thus-formed laminated structure (10A) is subjected to a heat treatment. Consequently, there can be obtained a silicon carbide semiconductor device which comprises an ohmic electrode that has good adhesion to a wiring line, while being suppressed in deposition of carbon atoms on the surface layer of the electrode and formation of an Schottky contact between Si and SiC.

公开(公告)号：CA2764900A1

公开(公告)日：2011-05-05

申请号：CA2764900

申请日：2010-09-27

Applicant: SUMITOMO ELECTRIC INDUSTRIES

Inventor： HARADA SHIN ,  SASAKI MAKOTO ,  NISHIGUCHI TARO ,  TAMASO HIDETO ,  NAMIKAWA YASUO

IPC: H01L21/02 ,  C30B29/36 ,  H01L21/20 ,  H01L21/205 ,  H01L21/336 ,  H01L29/12 ,  H01L29/78

Abstract: A method for manufacturing a silicon carbide substrate (1) includes the steps of: preparing a plurality of SiC substrates (20) each made of single-crystal silicon carbide; forming a base layer (10) made of silicon carbide and holding the plurality of SiC substrates (20), which are arranged side by side when viewed in a planar view; and forming a filling portion (60) filling a gap between the plurality of SiC substrates (20).