公开(公告)号：WO1989002080A1

公开(公告)日：1989-03-09

申请号：PCT/US1988002734

申请日：1988-08-08

Applicant: SUNDSTRAND DATA CONTROL, INC.

Inventor： SUNDSTRAND DATA CONTROL, INC. ,  HULSING, Rand, H., II ,  LEE, Charles, K.

IPC: G01R23/02

CPC classification number: G01R23/10

Abstract: A device and method for measuring the frequency of an input signal (I) by measuring the number of cycles of the input signal (I) that occur in a sample interval between successive sampling time tn. An integer counter (31) determines an estimated integer number of input signal cycles, and fraction counters (32, 33) determine fractional counts by counting cycles of a clock signal (CLK) during time intervals between a first measurement time before the sampling time and a second measurement time after the sampling time. A correction circuit (34) refines the fractional counts by determining the phase relationships between the clock (CLK) and input signals (I) at each measurement time. The correction circuit (56), a first switch (50) connected between the constant current source (52) and a reference potential, a second switch (54) connected between the control circuit (66) for the switches (50, 54). The control circuit (66) disconnects the current source (52) from the reference potential at each measurement time, and disconnects the current source (52) from the capacitor (56) upon the next occurrence of a periodic characteristic of the clock signal (CLK) that occurs after the measurement time. The voltage on the capacitor (56) then provides the required phase relationship.

公开(公告)号：WO1985004487A1

公开(公告)日：1985-10-10

申请号：PCT/US1985000445

申请日：1985-03-18

Applicant: SUNDSTRAND DATA CONTROL, INC.

Inventor： SUNDSTRAND DATA CONTROL, INC. ,  LEE, Charles, K. ,  PETERS, Rex, B. ,  GOGIC, Aleksander, M.

IPC: G01R23/00

CPC classification number: G01R23/10 ,  G01R23/02

Abstract: Prior techniques for determining frequency by counting the cycles of an input signal suffer from the limitation that counts are frequently lost between sampling intervals. This limitation is overcome by the present invention that provides an apparatus and method for counting the number of cycles of a sensor signal (FS) and of a reference signal (FR) that occur during respective sensor and reference intervals associate with a sampling interval defined by a sample signal (SAMPLE). The sensor, reference and sample signals are received by gating circuit (30) that generates a sensor gate signal (GATES) and a reference gate signal (GATER), the sensor and reference gate signals respectively defining the sensor and reference intervals. The sensor interval begins and ends synchronously with respect to the sensor signal, and the reference interval begins and ends synchronously with respect to the reference signal. The sensor, reference and sampling intervals are approximately co-extensive with one another. The apparatus further comprises a sensor court circuit (32) and a reference count circuit (34). The sensor count circuit counts cycles of the sensor signal that occur during the sensor interval, and the reference count circuit counts cycles of the reference signal that occur during the reference interval.

Abstract translation: 用于通过对输入信号的周期进行计数来确定频率的现有技术受到在采样间隔之间经常丢失计数的限制。 本发明克服了这个限制，本发明提供了一种用于计数传感器信号（FS）和参考信号（FR）的循环次数的装置和方法，该参考信号（FR）在相应的传感器和参考间隔期间发生，与由 采样信号（SAMPLE）。 传感器，参考和采样信号由生成传感器门信号（GATES）和参考门信号（GATER）的选通电路（30）接收，传感器和参考门信号分别定义传感器和参考间隔。 传感器间隔相对于传感器信号同步开始和结束，参考间隔相对于参考信号同步开始和结束。 传感器，参考和采样间隔彼此大致共同。 该装置还包括传感器法庭电路（32）和参考计数电路（34）。 传感器计数电路对传感器间隔期间发生的传感器信号的周期进行计数，参考计数电路计算参考时间段内发生的参考信号的周期。

公开(公告)号：EP0330693A1

公开(公告)日：1989-09-06

申请号：EP88907521.0

申请日：1988-08-08

Applicant: SUNDSTRAND DATA CONTROL, INC.

Inventor： HULSING, Rand, H., II ,  LEE, Charles, K.

IPC: G01R23

CPC classification number: G01R23/10

Abstract: A device and method for measuring the frequency of an input signal (I) by measuring the number of cycles of the input signal (I) that occur in a sample interval between successive sampling time t
n . An integer counter (31) determines an estimated integer number of input signal cycles, and fraction counters (32, 33) determine fractional counts by counting cy­ cles of a clock signal (CLK) during time intervals between a first measurement time before the sampling time and a second measurement time after the sampling time. A correction circuit (34) refines the fractional counts by determining the phase relationships between the clock (CLK) and input signals (I) at each measurement time. The correction circuit (56), a first switch (50) connected between the constant current source (52) and a reference potential, a second switch (54) connected between the control circuit (66) for the switches (50, 54). The control circuit (66) disconnects the current source (52) from the reference potential at each measurement time, and disconnects the current source (52) from the capacitor (56) upon the next occurrence of a periodic characteristic of the clock signal (CLK) that occurs after the measurement time. The voltage on the capacitor (56) then provides the required phase relationship.

Abstract translation: 通过测量在连续采样时间tn之间的采样间隔中出现的输入信号（I）的周期数来测量输入信号（I）的频率的设备和方法。 整数计数器（31）确定估计的整数个输入信号周期，并且分数计数器（32,33）通过计数时钟信号（CLK）的周期来确定分数计算， 在采样时间之前的第一测量时间与采样时间之后的第二测量时间之间的时间间隔期间。 校正电路（34）通过在每个测量时间确定时钟信号（CLK）与输入信号（I）之间的相位比率来细化分数计算。 校正电路34包括恒流源52，电容器56，连接在恒流源52和参考电位之间的第一开关50和第二开关54， ）连接在电源（52）和电容器（56）之间，以及用于开关（50,54）的控制电路（66）。 所述控制电路（66）断开的测量的各时刻的基准电位的电流源（52），并且一旦从所述冷凝器（56）断开电流源（52）作为再现的周期性特性 时钟信号（CLK），在测量时间之后发生。 电容器（56）中的电压然后提供必要的相位比。

公开(公告)号：EP0177557A1

公开(公告)日：1986-04-16

申请号：EP85901772.0

申请日：1985-03-18

Applicant: SUNDSTRAND DATA CONTROL, INC.

Inventor： LEE, Charles, K. ,  PETERS, Rex, B. ,  GOGIC, Aleksander, M.

IPC: G01R23

CPC classification number: G01R23/10 ,  G01R23/02

Abstract: Les techniques de l'art antérieur pour déterminer la fréquence par comptage des cycles d'un signal d'entrée sont limitées par le fait que les comptages sont fréquemment perdus entre les intervalles d'échantillonnage. Ce problème est résolu par la présente invention qui prévoit un appareil et un procédé du comptage du nombre de cycles d'un signal de détection (SS) et d'un signal de référence (SR) qui surviennent pendant des intervalles respectifs de détection et de référence associés à un intervalle d'échantillonnage déterminé par un signal d'échantillonnage (SAMPLE). Les signaux de détection, de référence et d'échantillonnage sont reçus par un circuit de séparation (30) produisant un signal de porte de détection (GATES) et un signal de porte de référence (GATER), les signaux de porte de détection et de référence déterminant respectivement les intervalles de détection et de référence. L'intervalle de détection débute et finit de manière synchrone par rapport au signal de détection et l'intervalle de référence débute et finit de manière synchrone par rapport au signal de référence. Les intervalles de détection, de référence et d'échantillonnage sont approximativement coétendus l'un avec l'autre. L'appareil comporte en outre un circuit de comptage de détection (32) et un circuit de comptage de référence (34). Le circuit de comptage de détection compte les cycles du signal de détection survenant pendant l'intervalle de détection, alors que le circuit de comptage de référence compte les cycles du signal de référence survenant pendant l'intervalle de référence.

Abstract translation: 通过对输入信号的周期进行计数来确定频率的现有技术受到在采样间隔之间频繁丢失计数的事实的限制。 该问题的本发明提供了一种装置和计数相应的间隔期间发生的，用于检测的传感器信号（SS）和参考信号（SR）的循环的数目的方法，并且通过求解 与由采样信号（SAMPLE）确定的采样间隔相关联的参考。 的检测信号，参比和样品由分离电路（30）产生一个检测选通信号（GATES）和参考用门信号（选通器），检测用栅极信号和接收到的 参考分别确定检测和参考区间。 检测间隔相对于检测信号同步地开始和结束，并且参考间隔相对于参考信号同步地开始和结束。 检测，参考和采样间隔大致相互延伸。 该装置还包括检测计数电路（32）和参考计数电路（34）。 检测计数电路对在检测间隔期间出现的检测信号的周期进行计数，而参考计数电路对在参考间隔期间出现的参考信号的周期进行计数。

公开(公告)号：EP0177557B1

公开(公告)日：1990-05-16

申请号：EP85901772.5

申请日：1985-03-18

Applicant: SUNDSTRAND DATA CONTROL, INC.

Inventor： LEE, Charles, K. ,  PETERS, Rex, B. ,  GOGIC, Aleksander, M.

IPC: G01R23/00

CPC classification number: G01R23/10 ,  G01R23/02

Abstract: Prior techniques for determining frequency by counting the cycles of an input signal suffer from the limitation that counts are frequently lost between sampling intervals. This limitation is overcome by the present invention that provides an apparatus and method for counting the number of cycles of a sensor signal (FS) and of a reference signal (FR) that occur during respective sensor and reference intervals associate with a sampling interval defined by a sample signal (SAMPLE). The sensor, reference and sample signals are received by gating circuit (30) that generates a sensor gate signal (GATES) and a reference gate signal (GATER), the sensor and reference gate signals respectively defining the sensor and reference intervals. The sensor interval begins and ends synchronously with respect to the sensor signal, and the reference interval begins and ends synchronously with respect to the reference signal. The sensor, reference and sampling intervals are approximately co-extensive with one another. The apparatus further comprises a sensor court circuit (32) and a reference count circuit (34). The sensor count circuit counts cycles of the sensor signal that occur during the sensor interval, and the reference count circuit counts cycles of the reference signal that occur during the reference interval.