公开(公告)号：JPH09114596A

公开(公告)日：1997-05-02

申请号：JP19305696

申请日：1996-07-23

Applicant: SYMBIOS LOGIC INC

Inventor： BURETSUTO ESU UEBAA

IPC: G06F3/06 ,  G06F13/40

Abstract: PROBLEM TO BE SOLVED: To improve throughput by transferring 1st data between a host device and a disk device through a 1st bus and transferring 2nd data between a processor and a controller resource without consuming any part of band width of 1st bus. SOLUTION: Data are sent from a disk drive 33 connected to a channel 32 through an input/output processor 24 to a DRAM 22 across a PCI local bus 28. In a processor 12, read data are sent from the DRAM 22 through a 2nd interface circuit 16 across the bus 28 to a host device 31. A 1st interface circuit 14 is provided with a circuit for interfacing the controller resource such as RAM or flash EPROM or the processor 12 connected to an auxiliary bus 38 such as ISA bus or any bus similar to it. Concerning data transfer to the processor 12, data are sent across a processor local bus 26.