公开(公告)号：JPH10126452A

公开(公告)日：1998-05-15

申请号：JP14481797

申请日：1997-06-03

Applicant: SYMBIOS LOGIC INC

Inventor： CHEN DAO-LONG

IPC: H03K19/0175 ,  H03K5/156 ,  H03K5/24 ,  H04L25/03

Abstract: PROBLEM TO BE SOLVED: To reduce distortion of a signal or to decrease jitter considerably depending on digital data in the case of decoding the digital data from the transmitted balanced signal. SOLUTION: A balanced signal includes a plurality of pulses of a 1st width. A receiver includes an input circuit 20, a buffer circuit 4, and a calibration circuit 60. The input circuit 20 includes a 1st differential amplifier to receive the signal and to amplify the 1st signal, a 2nd differential amplifier to amplify a 2nd signal, and a converter that receives the amplified 1st and 2nd signals to generate a 3rd signal. The buffer circuit receives the 3rd signal to butter the signal and provides an output of a 4th signal that includes a plurality of 2nd pulses having a plurality of 2nd pulse widths. The calibration circuit 60 receives the 4th signal, responds to it that the width of a plurality of the 2nd pulses is not equal to the width of the 1st pulse to generate a calibration signal. The calibration signal is received by the buffer circuit 40 to correct the 4th signal so that each width of a plurality of the 2nd pulses is nearly equal to the 1st pulse width.

公开(公告)号：EP0755135A3

公开(公告)日：1998-12-23

申请号：EP96305362

申请日：1996-07-22

Applicant: SYMBIOS LOGIC INC

Inventor： CHEN DAO-LONG

IPC: H03L7/06 ,  H03L7/07 ,  H03L7/099 ,  H04L7/033 ,  H03L7/22

CPC classification number: H03L7/0996 ,  H03L7/07 ,  H04L7/0337

Abstract: The invention provides for a method of recovering a clock signal embedded in an incoming data stream. The method includes the steps of providing the incoming data stream to a data sampler circuit (14) and first operating the data sampler circuit (14) to select one of a plurality of clock phases wherein the selected clock phase is indicative of the embedded clock signal, generating a recovered clock signal based on the selected clock phase and second, operating a retiming circuit (13) in a normal data tracking mode to retime the incoming data stream based on the recovered clock signal, and disabling operation of the data sampler circuit (14) while the retiming circuit (13) is operating in the normal data tracking mode. An apparatus for recovering a clock signal which is embedded in an incoming data stream is also provided.