公开(公告)号：JPH09181712A

公开(公告)日：1997-07-11

申请号：JP20844696

申请日：1996-08-07

Applicant: SYMBIOS LOGIC INC

Inventor： DAORON CHIEN

IPC: H03L7/095 ,  H03L7/089 ,  H03L7/091 ,  H03L7/099 ,  H04L7/033

Abstract: PROBLEM TO BE SOLVED: To provide a method for recovering data inside a phase locked loop(PLL) to be executed while using CMOS technique for high frequency serial data communication system by providing a specified data sampler. SOLUTION: An improved PLL circuit 20 has a clock generator 22 for generating five phase shift adjacent clock signals 23 sent through a path 24 to a sampler 26 for sampling the bits of input data 21 inputted to the data sampler 26. Two of five clock processing outputs 28 are sent to a phase detector 34 together with two of five clock signals 23, and phase control outputs 35a and 35b are sent to a charging pump 36 for accelerating or decelerating the speed of device 22 so as to control the phase of clock signal generated for the PLL. Clock processed data are sent from the PLL along a path 32 so as to be used at the other place of computer system, and the clock signal is similarly sent from the PLL through a path 27 as well.

公开(公告)号：JPH08228151A

公开(公告)日：1996-09-03

申请号：JP27412295

申请日：1995-10-23

Applicant: SYMBIOS LOGIC INC

Inventor： DAORON CHIEN

IPC: H03L7/22 ,  H03L7/08 ,  H03L7/081 ,  H03L7/087 ,  H03L7/23

Abstract: PROBLEM TO BE SOLVED: To realize a high frequency PLL circuit using a CMOS technique by connecting an exclusive OR circuit with the outputs of first and second PLL sub-circuits arranged in parallel. SOLUTION: A PLL sub-circuit 12 is triggered by the leading edge of a clock input from a crystal oscillator 18, and a PLL sub-circuit 14 is triggered by the trailing edge of the clock input. When a frequency-division ratio between frequency-dividers 20, 40 and frequency-dividers 32, 52 in the circuits 12 and 14 is set to be, for example, 2:11, and the frequency-division magnification of the frequency-dividers 32, 52 is set to be 1, and if a clock input frequency is set to be, for example, 100 MHz, signal frequencies at nodes A and B are 50 MHz, and signal frequencies at nodes C and D are increased to 550 MHz. Then, an exclusive OR circuit 16 which inputs signals at the nodes C and D outputs a 1.1 GHz clock signal with a frequency which is two times as high as that of the input signal when the phases of the both input signals are shifted by 90 deg..

公开(公告)号：JPH08102662A

公开(公告)日：1996-04-16

申请号：JP24401095

申请日：1995-09-22

Applicant: SYMBIOS LOGIC INC

Inventor： DAORON CHIEN

IPC: H03L1/00 ,  H03L7/08 ,  H03L7/18

Abstract: PROBLEM TO BE SOLVED: To operate in different feeding voltages with one PLL by detecting the value of power supply voltage to a PLL circuit and adjusting an operation frequency of the PLL circuit based on a detection value. SOLUTION: A detector detects the value of power supply voltage. An output 13 of the detector is connected to a PLL 14. The detector of power supply voltage operates by comparing the power supply voltage with reference voltage that is not affected by the power supply voltage. The PLL 14 includes a frequency divider 26 between Vco/ICO 24 and a phase detector 18. When it is detected that the power supply voltage is 5V as is shown by a control line 13, a multiplexer 28 selects an output 27 from the divider 26. In such cases, the frequency range of the PLL is adjusted based on the detected value of the power supply voltage by changing the reference voltage or reference current. This makes it possible to obtain a PLL which has an operation frequency characteristic that does not depend on power supply voltage.

公开(公告)号：JPH08195656A

公开(公告)日：1996-07-30

申请号：JP25881995

申请日：1995-10-05

Applicant: SYMBIOS LOGIC INC

Inventor： DAORON CHIEN

IPC: H03K5/13 ,  H03K3/017 ,  H03K3/03 ,  H03K3/354 ,  H03K5/156 ,  H03K19/00 ,  H03K19/0175

Abstract: PROBLEM TO BE SOLVED: To realize a circuit and method to generate a clock signal having the same frequency as that of a crystal whose duty cycle is adjusted to a stable duty cycle. SOLUTION: The circuit is made up of a clock generating circuit 16 connecting to a crystal 12 and converting a 1st signal from the crystal 12 into a clock signal and a duty cycle control circuit 18 that generates a feedback signal to change a duty cycle into a stable duty cycle. A clock control circuit 14 may have an output pad so as to decide the duty cycle with a measurement device.