METHOD AND APPARATUS FOR TRANSFER OF DATA IN CONTROLLER WITHINTEGRATED MEMORY

    公开(公告)号:JPH09128322A

    公开(公告)日:1997-05-16

    申请号:JP19305896

    申请日:1996-07-23

    Abstract: PROBLEM TO BE SOLVED: To improve the price/performance efficency of the controller by transferring 1st data between a memory device and a processor across a 1st and a 2nd bus according to the burst mode instruction execution cycle of the processor. SOLUTION: A 3rd interface circuit 18 functions as a PCI(periferal component interconnect) local bus master as to a device on a PCI local bus 28 and also functions as both the PCI bus master and a PCI bus slave for the processor 12. It is made possible to take burst mode code and data out through the 3rd interface circuit 18 across the PCI local bus 28, code/data caching capability is provided over the PCI local bus 28 through the 3rd interface circuit 18, and bandwidth is passed to an auxiliary bus 38 through an internal local bus 36.

    DISK ARRAY STORAGE SYSTEM CONTAINING HIGH-PERFORMANCE PARITYFUNCTION ARCHITECTURE

    公开(公告)号:JPH08235754A

    公开(公告)日:1996-09-13

    申请号:JP32869895

    申请日:1995-12-18

    Abstract: PROBLEM TO BE SOLVED: To improve the operating performance of a disk drive by providing an independent parity auxiliary engine and a local memory to an RA ID storage system so as to omit access to the disk drive required for parity calculation. SOLUTION: During disk write operation, data blocks received through a host SCSI channel 14 are stored in a local memory 136. A parity auxiliary engine 132 reads the data, calculates parity information and stores the result again to the local memory 136. Then a final data block is written to an adequate disk drive from the local memory 136. The local memory 136 consists of a DRAM or the like and is provided with a 72-bit interface to obtain economically a high frequency band. The parity auxiliary engine 132 uses a 128-byte FIFO to calculate the parity of the data in the local memory 136 in the unit of 1 burst at a time.

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