公开(公告)号：JPH08339329A

公开(公告)日：1996-12-24

申请号：JP12561396

申请日：1996-05-21

Applicant: SYMBIOS LOGIC INC

Inventor： RODONII EE DEKOUNINGU ,  DONARUDO AARU HAMURISETSUKU ,  MATSUKUSU ERU JIYONSON ,  KAATEISU DABURIYU RINKU

IPC: G06F12/08

Abstract: PROBLEM TO BE SOLVED: To optimize the performance of a host computer by generating a cache flashing parameter within the host computer to transfer to a controller and writing a large amount of writing request data from the cache memory of the controller according to the ache flashing parameter. SOLUTION: The host computer 10 and especially host adapters 14 and 16 are connected to each disk array controller 18 and 20 through independent buses such as host SCSI buses 28 and 30. A first controller 18 includes a data processor such as an old microprocessor, an input/output processor namely a subprocessor 32, a cache memory 33 and a cache battery 35. The cache memory 33 can be divided into a cache memory area 34 and an alternative cache memory area 36. A second controller 20 is similar to this.