公开(公告)号：AU5249298A

公开(公告)日：1998-06-03

申请号：AU5249298

申请日：1997-11-10

Applicant: SYMBIOS LOGIC INC

Inventor： MCMANUS MICHAEL J

IPC: H03K19/003 ,  H03K19/0185

Abstract: The present invention is directed to a low-power input buffer comprising an inverter coupled to receive a first safe voltage range to a first node and coupled to provide an output signal, and a low-power circuit coupled to receive a second safe voltage range and coupled to control a voltage at the first node in response to the output signal and the second safe voltage range. The first and second safe voltage ranges preferably are equivalent. The low-power circuit includes series transistors coupled to the first node and responsive to the voltage at the output node. The low-power circuit further includes a transistor coupled between the first and second nodes and responsive to an input voltage. A method of operating an input buffer comprises the steps of pulling up a voltage of a first node in response to voltages of a second node and an output node and pulling down the voltage at the first node and the second node in response to an input voltage to provide low power consumption and a high impedance input.

公开(公告)号：EP0716379A3

公开(公告)日：1998-08-19

申请号：EP95308860

申请日：1995-12-06

Applicant: SYMBIOS LOGIC INC

Inventor： BULLINGER PHILLIP W ,  MCMANUS MICHAEL J

IPC: G06F3/00 ,  H03K19/0175 ,  H03K19/0185 ,  G06F13/40

CPC classification number: H03K19/018521 ,  H03K19/018592

Abstract: The invention provides for an interface voltage control apparatus and method in which voltage levels of an external bus (PCI Vdd) are sampled with results stored to adjust both an output driver (16) and input receiver (18). The resulting logic signal levels for the input/output (I/O) interface are maintained within acceptable ranges of the standard I/O signal levels.