公开(公告)号：AU3184797A

公开(公告)日：1998-01-21

申请号：AU3184797

申请日：1997-06-23

Applicant: SYMBIOS LOGIC INC

Inventor： TABOR GREGORY A ,  JANDER MARK J

IPC: H03K3/03 ,  H03K5/13 ,  H03L7/099 ,  H03K19/003 ,  G06F13/40

Abstract: A precise timing delay method and apparatus. A phase-locked loop (PLL) in combination with a timing reference is used to calibrate a precise delay. These delays are then duplicated throughout the chip and controlled by the same current as in the PLL. This makes the delays process, voltage, and temperature insensitive. The delays can be programmed by selecting the desired delay through a multiplexer. Providing high precision delays are particularly advantageous for use in devices such as computer bus isolators.