公开(公告)号：EP0784274A3

公开(公告)日：1999-12-22

申请号：EP96309317.4

申请日：1996-12-19

Applicant: SYMBIOS LOGIC INC.

Inventor： DeKoning, Rodney A. ,  Humlicek, Donald R. ,  Rink, Curtis W.

IPC: G06F11/20 ,  G06F11/10 ,  G11B20/18

CPC classification number: G06F11/2094 ,  G06F11/1471 ,  G06F11/2089 ,  G06F11/2097 ,  G11B20/1883 ,  G11B2220/20

Abstract: The invention provides for a method and apparatus for increasing performance in a data processing system (100). The data processing system (100) includes a plurality of storage devices and a backup storage device (106) wherein the backup storage device (106) is configured as a log device. Data is logged to the backup storage device after the backup storage device has been configured as a log device. In response to a failure of a storage device within the plurality of storage devices, the backup storage device is reconfigured to be used as a replacement for the failed storage device

公开(公告)号：EP0717357A3

公开(公告)日：1997-05-28

申请号：EP95309117.0

申请日：1995-12-14

Applicant: SYMBIOS LOGIC INC.

Inventor： Stewart, John W. ,  Gates, Dennis E. ,  Dekoning, Rodney A. ,  Rink, Curtis W.

IPC: G06F11/10 ,  G11B20/18

CPC classification number: G06F11/1076 ,  G11B20/1833

Abstract: The invention provides for a high performance scalable hardware architecture for a disk array storage subsystem which supports RAID modes 0, 3, 4 and 5. The architecture features a high bandwidth parity calculation engine (132), a buffered PCI interface (130) operating at the full speed of a PCI bus (102), and a dedicated local memory (136). The dedicated local memory (136) is dual ported so that PCI and parity operations may operate concurrently. The architecture of the disk array controller allows parity calculations and memory block moves to occur without interfering with the controller processor or its associated memory, freeing the controller processor to manage array task control. The array controller configuration allows simultaneous operation of data block moves between storage I/O devices and local memory (136); data block moves between host SCSI connections and local memory; parity calculations; and normal CPU memory fetches, queued operations for block moves and queued operations for parity tasks.

公开(公告)号：EP0744696A1

公开(公告)日：1996-11-27

申请号：EP96303632.2

申请日：1996-05-21

Applicant: SYMBIOS LOGIC INC.

Inventor： Dekoning, Rodney A. ,  Johnson, Max L. ,  Humlicek, Donald R. ,  Rink, Curtis W.

IPC: G06F12/08

CPC classification number: G06F12/0804 ,  G06F12/0866

Abstract: The invention provides for a method of transferring data to a storage medium (39) arranged with a host computer (10) and which includes the steps of providing a controller (18) having a cache memory (33), generating a cache-flushing parameter in the host computer (10), transferring the cache-flushing parameter from the host computer (10) to the controller (18), and writing a quantity of write request data from the cache memory (33) of the controller (10) to the storage medium (39) in accordance with the cache-flushing parameter.

Abstract translation: 本发明提供一种将数据传送到与主计算机（10）一起布置的存储介质（39）的方法，并且包括以下步骤：提供具有高速缓存存储器（33）的控制器（18），产生高速缓冲存储器刷新参数 在所述主计算机（10）中，将所述主机计算机（10）的所述高速缓存刷新参数传送到所述控制器（18），并将所述写入请求数据从所述控制器（10）的高速缓冲存储器（33）写入到 所述存储介质（39）根据所述缓存刷新参数。

公开(公告)号：EP0717357A2

公开(公告)日：1996-06-19

申请号：EP95309117.0

申请日：1995-12-14

Applicant: SYMBIOS LOGIC INC.

Inventor： Stewart, John W. ,  Gates, Dennis E. ,  Dekoning, Rodney A. ,  Rink, Curtis W.

IPC: G06F11/10 ,  G11B20/18

CPC classification number: G06F11/1076 ,  G11B20/1833

Abstract: The invention provides for a high performance scalable hardware architecture for a disk array storage subsystem which supports RAID modes 0, 3, 4 and 5. The architecture features a high bandwidth parity calculation engine (132), a buffered PCI interface (130) operating at the full speed of a PCI bus (102), and a dedicated local memory (136). The dedicated local memory (136) is dual ported so that PCI and parity operations may operate concurrently. The architecture of the disk array controller allows parity calculations and memory block moves to occur without interfering with the controller processor or its associated memory, freeing the controller processor to manage array task control. The array controller configuration allows simultaneous operation of data block moves between storage I/O devices and local memory (136); data block moves between host SCSI connections and local memory; parity calculations; and normal CPU memory fetches, queued operations for block moves and queued operations for parity tasks.

Abstract translation: 本发明提供了用于支持RAID模式0,3,4和5的磁盘阵列存储子系统的高性能可扩展硬件架构。该架构具有高带宽奇偶校验计算引擎（132），缓冲PCI接口（130） PCI总线（102）的全速和专用本地存储器（136）。 专用本地存储器（136）是双端口的，使得PCI和奇偶校验操作可以同时操作。 磁盘阵列控制器的体系结构允许奇偶校验计算和存储块移动发生，而不会干扰控制器处理器或其相关联的存储器，释放控制器处理器来管理阵列任务控制。 阵列控制器配置允许在存储I / O设备和本地存储器之间的数据块移动的同时操作（136）; 数据块在主机SCSI连接和本地存储器之间移动; 奇偶计算; 和正常的CPU内存提取，用于块移动的排队操作和奇偶校验任务的排队操作。

公开(公告)号：EP0784274A2

公开(公告)日：1997-07-16

申请号：EP96309317.4

申请日：1996-12-19

Applicant: SYMBIOS LOGIC INC.

Inventor： DeKoning, Rodney A. ,  Humlicek, Donald R. ,  Rink, Curtis W.

IPC: G06F11/20 ,  G06F11/10 ,  G11B20/18

CPC classification number: G06F11/2094 ,  G06F11/1471 ,  G06F11/2089 ,  G06F11/2097 ,  G11B20/1883 ,  G11B2220/20

Abstract: The invention provides for a method and apparatus for increasing performance in a data processing system (100). The data processing system (100) includes a plurality of storage devices and a backup storage device (106) wherein the backup storage device (106) is configured as a log device. Data is logged to the backup storage device after the backup storage device has been configured as a log device. In response to a failure of a storage device within the plurality of storage devices, the backup storage device is reconfigured to be used as a replacement for the failed storage device

Abstract translation: 本发明提供一种用于提高数据处理系统（100）中的性能的方法和装置。 数据处理系统（100）包括多个存储装置和备用存储装置（106），其中备用存储装置（106）被配置为日志装置。 将备份存储设备配置为日志设备后，数据将记录到备份存储设备。 响应于多个存储设备内的存储设备的故障，备份存储设备被重新配置以用作故障存储设备的替换