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Patent Agency Ranking
公开(公告)号：JPH1041838A
公开(公告)日：1998-02-13
申请号：JP10073097
申请日：1997-03-13
Applicant: SYMBOL TECHNOLOGIES INC
Abstract: PROBLEM TO BE SOLVED: To provide a transceiver having a transmitter section and a receiver section by forming a modulator and a down converter on a single semiconductor body. SOLUTION: A transmitter section 12 and a receiver section 14 are formed on a single semiconductor body 51. The section 12 is provided with a modulator 22, transmission channel selector 24, frequency multiplier 26 and power amplifier 28, and the modulator 22 superimposes information from a microprocessor 18 onto the amplitude of any suitable radio-frequency carrier wave signal such as a microwave-frequency carrier wave signal. Moreover, the section 14 is provided with a low-noise amplifier 40, down converter 42 (equipped with a sample/hold circuit 43 and a low-pass filter 45), receiver channel selector 46, rough AGC circuit 48 and digital signal processor 50. The processor 50 performs automatic gain control and the amplitude adjustment of the digital signal, corresponding to the output of a demodulator 56.
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公开(公告)号：JPH1032517A
公开(公告)日：1998-02-03
申请号：JP10073297
申请日：1997-03-13
Applicant: SYMBOL TECHNOLOGIES INC
IPC: H04B1/40
Abstract: PROBLEM TO BE SOLVED: To provide a transceiver including a transmitter block and a receiver block. SOLUTION: A transmitter block includes a modulator 22 used to modulates data information on a carrier signal. A receiver block adopts a heterodyne system to convert the carrier into an intermediate frequency signal. The modulator 22 and the converter are formed on a single semiconductor chip. The receiver block receives a signal in a plurality of channels for a prescribed band width and a sampler samples the signal by a frequency lower than twice of the prescribed band width. The sampling frequency is selected so that the frequency of the selected channel is converted into a prescribed intermediate frequency and the frequency of the other channels is converted into a frequency higher than the intermediate frequency. The converted signal is converted into a digital signal. A demodulator 56 includes a Hilbert transformation versus filter block. A 1st AGC circuit adjusts the gain of an AGC circuit and a 2nd AGC circuit adjusts the amplitude of a digital signal.
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公开(公告)号：JP2002135154A
公开(公告)日：2002-05-10
申请号：JP2001290076
申请日：2001-08-20
Applicant: SYMBOL TECHNOLOGIES INC
IPC: H04B1/40
Abstract: PROBLEM TO BE SOLVED: To provide a transceiver which has a transmitter section and a receiver section. SOLUTION: In this transceiver, the transmitter section includes a modulator, which loads data information on a carrier signal and a receiver section converts the carrier to an intermediate frequency signal by a heterodyne system, with the modulator and the converter being built in on a single semiconductor chip. The receiver section receives signals in plural number of channels which have a stated band-width, a sampler samples with a sampling frequency of two times lower than the stated band width, and this frequency is selected, such that the frequency of selected channel is converted into the prescribed intermediate frequency. The other channel frequencies are converted into frequencies which are higher than the intermediate frequency, the converted signal is converted into a digital signal, a decoder includes a couple of Hilbert.transformasion and pair-filter sections, the first AGC circuit controls the gain of the AGC circuit, and the second circuit controls the amplitude of the digital signal.
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公开(公告)号：JPH10135791A
公开(公告)日：1998-05-22
申请号：JP10073197
申请日：1997-03-13
Applicant: SYMBOL TECHNOLOGIES INC
Abstract: PROBLEM TO BE SOLVED: To drive the gate of a PMOS transistor TR having a slower response earlier than the gate of an NMOS TR and to operate a ring oscillator with a higher oscillation frequency by using the differential amplifiers of a P and an N type inputs to plural cascaded inverters. SOLUTION: A PMOS TR 304' is not connected as an inverter and shares an NMOS TR that is contained in an inverter 3005 . An interpolation circuit 306' includes a pair of FET TR 305' and 307' whose drains age connected to the sources of a PMOS TR of the inverter 3005 and the TR 304' respectively. The delay is changed in two rings by the slow TR 304' and a fast NMOS TR included in the inverter 3005 . The circuit 306' mixes the inputs according to the control voltage which are applied to both TR 305' and 307' and changes the oscillation frequency of the VCO(voltage controlled oscillator) 38' and 76'.
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