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公开(公告)号：EP4546650A1
公开(公告)日：2025-04-30
申请号：EP24207764.2
申请日：2024-10-21
Applicant: Samsung Electronics Co., Ltd
Inventor： KANG, Pillseong , KIM, Chulho , YOO, Sangmin , LEE, Sangho , LEE, Joonhee , JO, Ikkyun
Abstract: A phase-locked loop (PLL) circuit comprising an oscillator including a first and a second capacitor cell array, each including a plurality of capacitor cells, and a control logic circuit connected to the oscillator. The control logic circuit configured to generate control code configured to control the oscillator such that the oscillator is configured to output a signal with a target frequency, the control code generated based on a first frequency of a first signal output from the oscillator and the target frequency, control at least some of capacitor cells included in the first capacitor cell array based on a first partial code generated based on a specified number of bits of the control code, and control at least some of capacitor cells included in the second capacitor cell array based on a second partial code generated based on bits other than the specified number of bits of the control code.
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公开(公告)号：EP4513762A1
公开(公告)日：2025-02-26
申请号：EP24194721.7
申请日：2024-08-15
Applicant: Samsung Electronics Co., Ltd
Inventor： LEE, Minseob , YOO, Sangmin , LEE, Joonhee , JO, Ikkyun , HAN, Honggul
Abstract: A phase-locked loop (PLL) circuit includes a voltage-controlled oscillator configured to generate an output clock signal of the PLL circuit, a phase detector configured to generate a phase error signal representing a phase difference between a first clock signal based on a reference clock signal and a second clock signal based on the output clock signal, a comparator configured to generate a phase error sign signal based on a reference voltage and the phase error signal, and a reference voltage generation circuit configured to scale first and second sign values of the phase error sign signal based on a fixed gain value and a variable gain value, respectively, and generate the reference voltage based on the scaled first and second sign values.
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3.发明公开
公开(公告)号：EP4518159A1
公开(公告)日：2025-03-05
申请号：EP24197021.9
申请日：2024-08-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： KANG, Pillseong , KIM, Chulho , LEE, Sangho , LEE, Joonhee , JO, Ikkyun
IPC: H03L7/099
Abstract: A phase-locked loop circuit includes an oscillator including a plurality of capacitor cells, and a control logic circuit that receives an output from the oscillator. The control logic circuit compares a target frequency with a first frequency of a first signal output from the oscillator, generates a first input code to control at least a portion of the plurality of capacitor cells to output a signal having the target frequency based on the comparison, generates a first output code corresponding to the first input code when the first input code is within a predetermined range of input codes, and controls at least two capacitor cells from among the plurality of capacitor cells based on the first output code. The oscillator may output a second signal having a second frequency through an electrical path including capacitor cells other than grounded capacitor cells from among the plurality of capacitor cells.
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