公开(公告)号：SG10202003748WA

公开(公告)日：2021-04-29

申请号：SG10202003748W

申请日：2020-04-24

Applicant: SAMSUNG ELECTRONICS CO LTD

Inventor： DOOHEE HWANG ,  TAEHUN KIM ,  MINKYUNG BAE ,  MYUNGHUN WOO ,  BONGYONG LEE

Abstract: A semiconductor device includes a source layer; a plurality of channel structures; a plurality of gate electrodes; and a common source line. At least one of the plurality of gate electrodes provides a GIDL line. For an erasing operation, an erasing voltage applied to the common source line reaches a target voltage, and, after the erasing voltage reaches the target voltage, a step increment voltage is applied to the erasing voltage, such that the erasing voltage has a voltage level higher than a voltage level of the target voltage. After the step increment voltage has been applied for a desired time period, the voltage level of the erasing voltage is decreased to the target voltage level for the remainder of the erasing operation.

公开(公告)号：US20200020717A1

公开(公告)日：2020-01-16

申请号：US16265688

申请日：2019-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： BONGYONG LEE ,  TAE HUN KIM ,  Minkyung BAE

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11556

Abstract: A three-dimensional (3D) semiconductor memory device may include a stack structure including gate electrodes sequentially stacked on a substrate, and a vertical channel penetrating the stack structure. The gate electrodes may include a ground selection gate electrode, a cell gate electrode, a string selection gate electrode, and an erase gate electrode, which are sequentially stacked on the substrate.