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    Three-dimensional semiconductor memory devices
    5.
    发明授权
    Three-dimensional semiconductor memory devices 有权

    公开(公告)号：US09356159B2

    公开(公告)日：2016-05-31

    申请号：US14830299

    申请日：2015-08-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Changhyun Lee ,  Byoungkeun Son ,  Hyejin Cho

    IPC: H01L27/115 ,  H01L29/792

    CPC classification number: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/7926

    Abstract: Three-dimensional (3D) nonvolatile memory devices include a substrate having a well region of second conductivity type (e.g., P-type) therein and a common source region of first conductivity type (e.g., N-type) on the well region. A recess extends partially (or completely) through the common source region. A vertical stack of nonvolatile memory cells on the substrate includes a vertical stack of spaced-apart gate electrodes and a vertical active region, which extends on sidewalls of the vertical stack of spaced-apart gate electrodes and on a sidewall of the recess. Gate dielectric layers extend between respective ones of the vertical stack of spaced-apart gate electrodes and the vertical active region. The gate dielectric layers may include a composite of a tunnel insulating layer, a charge storage layer, a relatively high bandgap barrier dielectric layer and a blocking insulating layer having a relatively high dielectric strength.

    Three-Dimensional Semiconductor Devices and Methods of Fabricating the Same
    6.
    发明申请
    Three-Dimensional Semiconductor Devices and Methods of Fabricating the Same 审中-公开
    三维半导体器件及其制造方法

    公开(公告)号：US20150037951A1

    公开(公告)日：2015-02-05

    申请号：US14515997

    申请日：2014-10-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sung-IL Il Chang ,  Changhyun Lee ,  Byoungkeun Son ,  Jin-Soo Lim

    IPC: H01L27/115 ,  H01L21/311 ,  H01L21/02

    CPC classification number: H01L27/11582 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/31111 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11556 ,  H01L29/4232 ,  H01L29/42372

    Abstract: Three-dimensional semiconductor devices are provided. The three-dimensional semiconductor device includes a substrate, a buffer layer on the substrate. The buffer layer includes a material having an etching selectivity relative to that of the substrate. A multi-layer stack including alternating insulation patterns and conductive patterns is provided on the buffer layer opposite the substrate. One or more active patterns respectively extend through the alternating insulation patterns and conductive patterns of the multi-layer stack and into the buffer layer. Related fabrication methods are also discussed.

    Abstract translation: 提供三维半导体器件。 三维半导体器件包括衬底，衬底上的缓冲层。 缓冲层包括具有相对于衬底的蚀刻选择性的材料。 在与衬底相对的缓冲层上提供包括交替绝缘图案和导电图案的多层堆叠。 一个或多个有源图案分别延伸穿过多层堆叠的交替绝缘图案和导电图案并进入缓冲层。 还讨论了相关的制造方法。

    NONVOLATILE MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME
    7.
    发明申请
    NONVOLATILE MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME 有权
    非易失性存储器件及其编程方法

    公开(公告)号：US20130176792A1

    公开(公告)日：2013-07-11

    申请号：US13734247

    申请日：2013-01-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Changhyun Lee

    IPC: G11C16/14

    CPC classification number: G11C16/14 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483

    Abstract: A nonvolatile memory device and a method of programming the same. The nonvolatile memory device includes a memory cell array including a plurality of memory cells and a program control logic circuit controlling the memory cell array. The program control logic circuit programs a first memory cell so that the threshold voltage of the first memory cell corresponding to data of erasure state is higher than the threshold voltage of a second memory cell corresponding to data of program state, in the memory cell array. The nonvolatile memory device controlled in this manner can provide higher reliability.

    Abstract translation: 非易失性存储器件及其编程方法。 非易失性存储器件包括包括多个存储单元的存储单元阵列和控制存储单元阵列的程序控制逻辑电路。 程序控制逻辑电路对第一存储器单元进行编程，使得与擦除状态数据相对应的第一存储单元的阈值电压高于存储单元阵列中对应于程序状态数据的第二存储单元的阈值电压。 以这种方式控制的非易失性存储器件可以提供更高的可靠性。

    Cooking appliance
    8.
    发明授权
    Cooking appliance 有权

    公开(公告)号：US12193132B2

    公开(公告)日：2025-01-07

    申请号：US17315021

    申请日：2021-05-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Changhyun Lee ,  Seunghee Cho

    IPC: H05B6/64 ,  F24C15/00 ,  F24C15/20

    Abstract: Provided is a cooking appliance including a grille frame with a filter fixing structure. The cooking appliance includes: a cabinet; a hood flow path formed inside the cabinet; a blower positioned in the cabinet to form an air flow inside the hood flow path; a filter positioned on the hood flow path to filter the air flow supplied from the blower; and a grille frame including an outlet discharging filtered air to an outside of the cabinet, and forming a plurality of support spaces, wherein a lower end of the filter is inserted in and supported by one support space of the plurality of support spaces.

    Three-dimensional semiconductor memory devices
    9.
    发明授权
    Three-dimensional semiconductor memory devices 有权

    公开(公告)号：US10978479B2

    公开(公告)日：2021-04-13

    申请号：US16804982

    申请日：2020-02-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Changhyun Lee ,  Byoungkeun Son ,  Hyejin Cho

    IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/792

    Abstract: Three-dimensional (3D) nonvolatile memory devices include a substrate having a well region of second conductivity type (e.g., P-type) therein and a common source region of first conductivity type (e.g., N-type) on the well region. A recess extends partially (or completely) through the common source region. A vertical stack of nonvolatile memory cells on the substrate includes a vertical stack of spaced-apart gate electrodes and a vertical active region, which extends on sidewalls of the vertical stack of spaced-apart gate electrodes and on a sidewall of the recess. Gate dielectric layers extend between respective ones of the vertical stack of spaced-apart gate electrodes and the vertical active region. The gate dielectric layers may include a composite of a tunnel insulating layer, a charge storage layer, a relatively high bandgap barrier dielectric layer and a blocking insulating layer having a relatively high dielectric strength.

    Three-dimensional semiconductor memory devices
    10.
    发明授权
    Three-dimensional semiconductor memory devices 有权

    公开(公告)号：US10600801B2

    公开(公告)日：2020-03-24

    申请号：US15871375

    申请日：2018-01-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Changhyun Lee ,  Byoungkeun Son ,  Hyejin Cho

    IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/792

    Abstract: Three-dimensional (3D) nonvolatile memory devices include a substrate having a well region of second conductivity type (e.g., P-type) therein and a common source region of first conductivity type (e.g., N-type) on the well region. A recess extends partially (or completely) through the common source region. A vertical stack of nonvolatile memory cells on the substrate includes a vertical stack of spaced-apart gate electrodes and a vertical active region, which extends on sidewalls of the vertical stack of spaced-apart gate electrodes and on a sidewall of the recess. Gate dielectric layers extend between respective ones of the vertical stack of spaced-apart gate electrodes and the vertical active region. The gate dielectric layers may include a composite of a tunnel insulating layer, a charge storage layer, a relatively high bandgap barrier dielectric layer and a blocking insulating layer having a relatively high dielectric strength.

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