APPARATUS INCLUDING SM IN WIRELESS COMMUNICATION SYSTEM

    公开(公告)号:US20250167816A1

    公开(公告)日:2025-05-22

    申请号:US18950445

    申请日:2024-11-18

    Abstract: The disclosure relates to a 5G or 6G communication system for supporting a data transmission rate higher than a 4G communication system such as LTE. An electronic device in a wireless communication system may include a PA and an SM configured to supply power to the PA, wherein the SM may include a linear SM to which a signal for an envelope tracking (ET) is input, and a first SM connected to the linear SM and comprising a first converter for direct current (DC)-DC conversion and at least one lumped element connected to the first converter, and the first SM may be configured to convert the signal for the ET into a first digital signal, to generate a first control signal for the first converter based on a change of a voltage value of the first digital signal, to generate a second digital signal by delaying the first digital signal by a predetermined clock, and to control the at least one lumped element based on the first digital signal and the second digital signal to adjust a current output from the first SM.

    LOW NOISE AMPLIFIER AND RECEIVER USING SAME IN WIRELESS COMMUNICATION SYSTEM

    公开(公告)号:US20240333321A1

    公开(公告)日:2024-10-03

    申请号:US18615412

    申请日:2024-03-25

    CPC classification number: H04B1/0078 H04B1/04 H04B2001/0408

    Abstract: The present disclosure relates to a 5G communication system or a 6G communication system for supporting higher data rates beyond a 4G communication system such as long term evolution (LTE). A low noise amplifier (LNA) in a wireless communication system according to an embodiment of the disclosure includes a first transistor and a first feedback transformer in which a gate of the first transistor is connected to a primary coil of the first feedback transformer and a source of the first transistor is connected to a secondary coil of the first feedback transformer. The first feedback transformer is configured to implement positive feedback to maintain an in-phase signal at the gate of the first transistor and the source of the first transistor.

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