公开(公告)号：US20240324243A1

公开(公告)日：2024-09-26

申请号：US18473660

申请日：2023-09-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongjae KIM ,  Woojin KIM ,  Junghoon BAK ,  Hyunchul SHIN ,  Hyeonah JO

IPC: H10B61/00 ,  H01L23/522

CPC classification number: H10B61/22 ,  H01L23/5226

Abstract: A semiconductor device includes a plurality of data storage patterns on a substrate, the plurality of data storage patterns spaced apart from each other in a first direction parallel to an upper surface of the substrate, a first upper conductive line on the plurality of data storage patterns, extending in the first direction and connected to the plurality of data storage patterns, a second upper conductive line on the first upper conductive line and extending in the first direction and a plurality of via contacts between the first upper conductive line and the second upper conductive line and spaced apart from each other in the first direction. The plurality of via contacts are arranged to be offset from the plurality of data storage patterns in the first direction.

公开(公告)号：US20250107102A1

公开(公告)日：2025-03-27

申请号：US18620469

申请日：2024-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhoe KIM ,  Kilho LEE ,  Shin KWON ,  Hyeonah JO

IPC: H10B61/00 ,  G01R33/09 ,  H10N50/10

Abstract: A semiconductor device includes a substrate including a cell region and a peripheral region, a first lower insulating layer disposed on the cell region and extending onto the peripheral region, a second lower insulating layer disposed on the first lower insulating layer on the cell region and extending onto the first lower insulating layer on the peripheral region, data storage patterns disposed on the second lower insulating layer on the cell region, a cell insulating layer disposed on the second lower insulating layer on the cell region and covering the data storage patterns, and a peripheral insulating layer disposed on the second lower insulating layer on the peripheral region and including a material different from the cell insulating layer. A thickness of the second lower insulating layer on the peripheral region is smaller than a maximum thickness of the second lower insulating layer on the cell region.