公开(公告)号：US20240072007A1

公开(公告)日：2024-02-29

申请号：US18331973

申请日：2023-06-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： In Lee ,  Taeyoung Kim

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2924/381

Abstract: A semiconductor package includes a base substrate, a first semiconductor chip mounted on the base substrate, and a second semiconductor chip mounted on the first semiconductor chip. The first semiconductor includes first conductive connection structures that have a first pitch interval in a first direction and a second pitch interval in a second direction, and the second semiconductor chip includes second conductive connection structures that have the first pitch interval in the first direction and the second pitch interval in the second direction. The first conductive connection structures include first power connection structures, first ground connection structures, and first dummy structures. The first ground connection structure or the first dummy structure is between two first power connection structures neighboring in the first direction and between two first power connection structures neighboring in the second direction among the first power connection structures.

公开(公告)号：US09165897B2

公开(公告)日：2015-10-20

申请号：US14028534

申请日：2013-09-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： In Lee

IPC: H01L23/00 ,  H01L25/065 ,  G11C5/02 ,  H01L23/50 ,  H01L23/538 ,  H01L25/18

CPC classification number: H01L24/06 ,  G11C5/02 ,  H01L23/50 ,  H01L23/5386 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L24/49 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06155 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/17155 ,  H01L2224/32145 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/49176 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A semiconductor package includes one or more semiconductor stack structures mounted on a package board. The semiconductor stack structures include sequentially stacked first to fourth semiconductor devices. Each of the first to fourth semiconductor devices includes a first unit semiconductor chip and a second unit semiconductor chip. The first unit semiconductor chip and the second unit semiconductor chip are unitary. A method for fabricating the semiconductor package includes forming pairs of unit semiconductor chips on a wafer, forming a scribe lane between the pairs of unit semiconductor chips, separating the pairs of unit semiconductor chips into semiconductor devices, each of the semiconductor devices having a corresponding one pair of unit semiconductor chips.

Abstract translation: 半导体封装包括安装在封装板上的一个或多个半导体堆叠结构。 半导体堆叠结构包括顺序堆叠的第一至第四半导体器件。 第一至第四半导体器件中的每一个包括第一单元半导体芯片和第二单元半导体芯片。 第一单元半导体芯片和第二单元半导体芯片是一体的。 一种用于制造半导体封装的方法，包括在晶片上形成单元半导体芯片对，在成对的单位半导体芯片之间形成划线，将成对的单位半导体芯片分离成半导体器件，每个半导体器件具有相应的一个 一对单位半导体芯片。

公开(公告)号：US10157883B2

公开(公告)日：2018-12-18

申请号：US15404090

申请日：2017-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chul Park ,  Kilsoo Kim ,  In Lee

IPC: H01L25/065 ,  H01L23/00

Abstract: A semiconductor package comprises a package substrate; a first chip stack and a second chip stack mounted side by side on the package substrate, wherein the first and second chip stacks each include a plurality of semiconductor chips stacked on the package substrate, wherein each of the semiconductor chips includes a plurality of bonding pads provided on a respective edge region thereof, wherein at least some of the plurality of bonding pads are functional pads, and wherein the functional pads occupy a region that is substantially less than an entirety of the respective edge region.

公开(公告)号：US08803311B2

公开(公告)日：2014-08-12

申请号：US13836937

申请日：2013-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： In Lee ,  Kilsoo Kim

IPC: H01L23/12

CPC classification number: H05K1/0298 ,  H01L23/49816 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K3/4608 ,  H05K2201/10416 ,  H01L2924/00

Abstract: A wiring board and a semiconductor package are provided. The wiring board includes: a metal core including a first surface and a second surface opposite the first surface; a first buildup portion and a second buildup portion including an insulating layer and a pad pattern sequentially stacked, the first and second buildup portions being provided on the first surface and the second surface, respectively; a mask pattern including an opening exposing the pad pattern, the mask pattern being provided on the second buildup portion; and a barrier pattern in an area in which a region of the metal core which overlaps with the pad pattern of the second buildup portion is removed, wherein a minimum width of an outer circumference of the barrier pattern is greater than a maximum width of the pad pattern of the second buildup portion.

Abstract translation: 提供了布线板和半导体封装。 布线板包括：金属芯，包括第一表面和与第一表面相对的第二表面; 第一累积部分和第二累积部分，其包括依次层叠的绝缘层和焊盘图案，所述第一和第二累积部分别分别设置在所述第一表面和所述第二表面上; 掩模图案，包括露出所述焊盘图案的开口，所述掩模图案设置在所述第二堆积部分上; 以及其中去除与第二积累部分的焊盘图案重叠的金属芯的区域的区域中的阻挡图案，其中阻挡图案的外周的最小宽度大于焊盘的最大宽度 第二累积部分的图案。