公开(公告)号：US20240321679A1

公开(公告)日：2024-09-26

申请号：US18505412

申请日：2023-11-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngjoon KOH ,  Jaechoon KIM

IPC: H01L23/427 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L23/427 ,  H01L25/18 ,  H10B80/00 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05169 ,  H01L2224/05184 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/1441 ,  H01L2924/1443

Abstract: A heat dissipation structure may include a heat dissipation chamber including a lower wall, an upper wall on the lower wall, and a plurality of sidewalls extending between the lower wall and the upper wall, the heat dissipation chamber providing an inner space for a working fluid to flow therein; and a wick structure on an inner surface of the heat dissipation chamber. The wick structure may be configured to guide the working fluid in a liquid state. The heat dissipation chamber may be configured to change its shape according to a temperature.

公开(公告)号：US20240321841A1

公开(公告)日：2024-09-26

申请号：US18609255

申请日：2024-03-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwanjoo PARK ,  Jaechoon KIM ,  Sunggu KANG ,  Taehwan KIM

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/373 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L25/105 ,  H01L23/3128 ,  H01L23/3736 ,  H01L23/49816 ,  H01L23/5383 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1094

Abstract: The disclosure provides a semiconductor package including a first wiring structure including a first wiring, a first semiconductor chip on the first wiring structure, a molding member surrounding the first semiconductor chip, a second wiring structure on an upper surface of the molding member and including a second wiring and a heat conductive metal, a second semiconductor chip on an upper surface of the second wiring structure, a plurality of first bumps between the second wiring structure and the second semiconductor chip, an underfill layer covering the plurality of first bumps, and a first thermal interface material (TIM) on an upper surface of the heat conductive metal, the heat conductive metal not overlapping the plurality of first bumps in the vertical direction.

公开(公告)号：US20240014166A1

公开(公告)日：2024-01-11

申请号：US18218886

申请日：2023-07-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngdeuk KIM ,  Jaechoon KIM ,  Taehwan KIM ,  Kyungsuk OH ,  Heejung Hwang

IPC: H01L23/00 ,  H01L25/18 ,  H10B80/00 ,  H01L25/00

CPC classification number: H01L24/73 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/33 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/18 ,  H10B80/00 ,  H01L25/50 ,  H01L2224/05025 ,  H01L2224/05155 ,  H01L2224/05073 ,  H01L2224/05564 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05666 ,  H01L2224/06181 ,  H01L2224/05647 ,  H01L2224/80359 ,  H01L2924/0544 ,  H01L2924/059 ,  H01L2224/06505 ,  H01L2224/08145 ,  H01L2224/13111 ,  H01L2224/13109 ,  H01L2224/13113 ,  H01L2224/1312 ,  H01L2224/13147 ,  H01L2224/13139 ,  H01L2224/13118 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2924/014 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32013 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/80357 ,  H01L2224/81203 ,  H01L2224/83203 ,  H01L2224/9211 ,  H01L2224/92222 ,  H01L2224/92242 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/9222

Abstract: A semiconductor package including: a lower chip; a chip structure including stacked semiconductor chips; and an adhesive film, the semiconductor chips include first bonding chips bonded to each other by bumps and second bonding chips directly bonded to each other, the first bonding chips include: a first bonding lower chip including a first bonding upper pad; and a first bonding upper chip on the first bonding lower chip and including a first bonding lower pad, the second bonding chips include: a second bonding lower chip including a second bonding upper insulating layer and a second bonding upper pad; and a second bonding upper chip on the second bonding lower chip and including a second bonding lower insulating layer, and a second bonding lower pad, and the adhesive film surrounds side surfaces of the bumps, fills a region between the first bonding lower and upper chips, and protrudes from the region.

公开(公告)号：US20240145360A1

公开(公告)日：2024-05-02

申请号：US18244997

申请日：2023-09-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hwanjoo PARK ,  Jaechoon KIM ,  Sunggu KANG ,  Eunho CHO ,  Taehwan KIM ,  Jonggyu LEE

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L23/49811 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2924/1434

Abstract: A semiconductor package includes a first redistribution wiring layer having first redistribution wirings, a first semiconductor chip on the first redistribution wiring layer and having a first thickness from the first redistribution wiring layer, a second semiconductor chip disposed on the first redistribution wiring layer spaced apart from the first semiconductor chip and having a second thickness from the first redistribution wiring layer smaller than the first thickness, a sealing member covering the first semiconductor chip and the second semiconductor chip on the first redistribution wiring layer, a plurality of conductive vias provided in the sealing member and electrically connected to the first redistribution wirings, a second redistribution wiring layer disposed on the sealing member and having second redistribution wirings electrically connected to the conductive vias, and at least one third semiconductor chip disposed on the second redistribution wiring layer and electrically connected to the second redistribution wirings.

公开(公告)号：US20230307318A1

公开(公告)日：2023-09-28

申请号：US18066861

申请日：2022-12-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jonggyu LEE ,  Sunggu KANG ,  Jaechoon KIM ,  Taehwan KIM ,  Hwanjoo PARK ,  Kyungsuk OH

IPC: H01L23/473 ,  H01L25/18 ,  H01L23/538 ,  H01L23/31

CPC classification number: H01L23/473 ,  H01L25/18 ,  H01L23/5385 ,  H01L23/3128

Abstract: A semiconductor package includes a package substrate; an interposer on the package substrate; a first semiconductor chip on the interposer; at least one second semiconductor chip on the interposer; a molding layer extending around the first semiconductor chip and the at least one second semiconductor chip; a barrier layer on the upper surface of the molding layer; a separation wall on the barrier layer, the separation wall configured to define a first cooling space adjacent the first semiconductor chip and a second cooling space adjacent the at least one second semiconductor chip; and a heat dissipation structure on the separation wall, wherein the heat dissipation structure provides a cooling channel through which the cooling fluid flows.

公开(公告)号：US20250140695A1

公开(公告)日：2025-05-01

申请号：US18927458

申请日：2024-10-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunggu KANG ,  Jaechoon KIM ,  Sungho MUN

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/48 ,  H01L23/498 ,  H01L25/065 ,  H10B80/00

Abstract: A semiconductor package includes a first redistribution layer substrate having a lower conductive structure; a first semiconductor chip and a second semiconductor chip electrically connected to the first redistribution layer substrate and arranged side-by-side on the first redistribution layer substrate; and an interposer disposed over a portion of the first semiconductor chip and a portion of the second semiconductor chip to electrically connect the first semiconductor chip to the second semiconductor chip, wherein the first semiconductor chip comprises a rear power distribution network structure in a lower portion of the first semiconductor chip, and the second semiconductor chip comprises a rear power distribution network structure in a lower portion of the second semiconductor chip.

公开(公告)号：US20240332150A1

公开(公告)日：2024-10-03

申请号：US18401872

申请日：2024-01-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwanjoo PARK ,  Sunggu KANG ,  Jaechoon KIM

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/367 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L23/49822 ,  H01L23/367 ,  H01L23/481 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0652 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/1431

Abstract: A semiconductor package includes a first redistribution wiring layer having first redistribution wirings; a first lower semiconductor chip and a second lower semiconductor chip spaced apart from each other on the first redistribution wiring layer; a sealing member covering the first lower semiconductor chip and the second lower semiconductor chip on the first redistribution wiring layer; a plurality of conductive vias penetrating the sealing member between the first lower semiconductor chip and the second lower semiconductor chip; a second redistribution wiring layer disposed on the sealing member and having second redistribution wirings electrically connected to the plurality of conductive vias; an upper semiconductor chip disposed on the second redistribution wiring layer and electrically connected to the second redistribution wirings; and a first heat dissipation block and a second heat dissipation block respectively disposed on the first lower semiconductor chip and the second lower semiconductor chip.

公开(公告)号：US20240186290A1

公开(公告)日：2024-06-06

申请号：US18236024

申请日：2023-08-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taehwan KIM ,  Youngdeuk KIM ,  Jaechoon KIM ,  Kyungsuk OH ,  Jonggyu LEE ,  Mina CHOI

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/522

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06541

Abstract: A semiconductor package includes electrically connected first to third semiconductor chips, stacked in a vertical direction; an encapsulant on the first semiconductor chip and encapsulating a portion of each of the semiconductor chips; and external connection bumps below the first semiconductor chip and being electrically connected to the semiconductor chips, wherein the semiconductor chips each include a plurality of lower pads, the first and second semiconductor chips each include a plurality of upper pads including a first group of upper pads and a second group of upper pads, and through-electrodes electrically respectively connecting the upper pads and the lower pads, and the through-electrodes include a first group of through-electrodes respectively connected to the first group of upper pads, and a second group of through-electrodes connected to upper pads that are electrically connected to each other of the second group of upper pads.

公开(公告)号：US20230178450A1

公开(公告)日：2023-06-08

申请号：US17892252

申请日：2022-08-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungeun JO ,  Jaemin JUNG ,  Jaechoon KIM ,  Seunggeol RYU ,  Kyungsuk OH

IPC: H01L23/367 ,  H01L23/528

CPC classification number: H01L23/367 ,  H01L23/5283

Abstract: A film package, includes: a film substrate having first and second surfaces opposing each other; a plurality of wiring patterns respectively including an input pattern, an output pattern, and an interconnection pattern; a first semiconductor chip electrically connected to the input pattern and the interconnection pattern; a second semiconductor chip electrically connected to the interconnection pattern and the output pattern; a protective layer on the first surface to cover at least a portion of the plurality of wiring patterns; a first conductive film on the protective layer and extending in a second direction; and a second conductive film on the second surface to overlap the first conductive film in a third direction.