公开(公告)号：US20250046619A1

公开(公告)日：2025-02-06

申请号：US18791926

申请日：2024-08-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Guifu Yang ,  Sunghwan Jang ,  Sanghyeon Kim ,  Jinbum Kim ,  Hanhum Park ,  Sunguk Jang

IPC: H01L21/3115 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3213

Abstract: A method of manufacturing a semiconductor apparatus includes forming a target layer, a bottom mask layer including a first mask, and a photoresist pattern, on a substrate; contracting the photoresist pattern; forming a mandrill bar on the first mask layer using the photoresist pattern that had been contracted; forming a conformal spacer layer on the first mask and the mandrill bar; etching the spacer layer such that at least a portion of the first mask is free of the spacer layer; forming a sacrificial layer on the at least the portion of the first mask; forming a hard-mask bar by etching the spacer layer and the first mask; and patterning the target layer using the hard-mask bar.

公开(公告)号：US20240322039A1

公开(公告)日：2024-09-26

申请号：US18421001

申请日：2024-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyojin Kim ,  Jinbum Kim ,  Sangmoon Lee ,  Yongjun Nam ,  Ingeon Hwang

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/7848 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/78696 ,  H01L29/42392

Abstract: The integrated circuit device includes a fin-type active region extending in a first direction, a channel region on the fin-type active region, a gate line on the channel region and extending in a second direction, and a source/drain region on the fin-type active region and in contact with the channel region, wherein the source/drain region includes a plurality of semiconductor layers including a first semiconductor layer that includes a portion in contact with the channel region and a portion in contact with the fin-type active region, a second semiconductor layer on the first semiconductor layer, and a third semiconductor layer on the second semiconductor layer, a germanium (Ge) content ratio in the first semiconductor layer is greater than or equal to 10 at % and less than 100 at %, and the Ge content ratio in the first semiconductor layer decreases towards a boundary with the second semiconductor layer.

公开(公告)号：US20240321885A1

公开(公告)日：2024-09-26

申请号：US18476688

申请日：2023-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinbum Kim ,  Ingyu Jang ,  Sujin Jung ,  Gyeom Kim ,  Hyojin Kim ,  Yongjun Nam ,  Sangmoon Lee

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/823814 ,  H01L21/823871

Abstract: An integrated circuit device includes a first transistor comprising a first conductivity type, which includes a first channel region and a first source/drain region, a second transistor comprising a second conductivity type, which includes a second channel region and a second source/drain region, a first contact structure that contacts the first source/drain region and comprising a first length, and the first contact structure extends from above the first source/drain region and beyond an uppermost surface of the first channel region by a first vertical distance, and a second contact structure that contacts the second source/drain region and having a second length that is greater than the first length, the second contact extends from above the second source/drain region and beyond an uppermost surface of the second channel region by a second vertical distance, which is greater than the first vertical distance.

公开(公告)号：US20240258410A1

公开(公告)日：2024-08-01

申请号：US18531836

申请日：2023-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongwoo Kim ,  Jinbum Kim

IPC: H01L29/732 ,  H01L23/528 ,  H01L29/66

CPC classification number: H01L29/7325 ,  H01L23/5286 ,  H01L29/66287

Abstract: A semiconductor device includes a substrate having a recessed region, a first semiconductor region including a first semiconductor layer on a bottom surface and an inner side surface of the recessed region and a first protrusion on the first semiconductor layer, and having a first conductivity type, a second semiconductor region including a second semiconductor layer on the first semiconductor layer and a second protrusion on the second semiconductor layer, and having a second conductivity type, a third semiconductor region including a third semiconductor layer on the second semiconductor layer and a third protrusion on the third semiconductor layer, and having the first conductivity type, a epitaxial stopper layer covering the bottom surface of the recessed region between the first semiconductor region and the substrate and including a material different from materials of the first semiconductor region, and a dummy gate structure intersecting the first to third protrusions on the substrate.

公开(公告)号：US11984507B2

公开(公告)日：2024-05-14

申请号：US17206229

申请日：2021-03-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongwoo Kim ,  Jinbum Kim ,  Gyeom Kim ,  Dohee Kim ,  Seunghun Lee

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/06 ,  H01L29/161 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/78618 ,  H01L21/02532 ,  H01L21/02603 ,  H01L29/0673 ,  H01L29/161 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/78696

Abstract: A semiconductor device including an active region extending in a first direction on a substrate; channel layers vertically spaced apart on the active region; a gate structure extending in a second direction and intersecting the active region, the gate structure surrounding the channel layers; a source/drain region on the active region in contact with the channel layers; and a contact plug connected to the source/drain region, wherein the source/drain region includes a first epitaxial layer on side surfaces of the channel layers and including a first impurity; a second epitaxial layer on the first epitaxial layer and including the first impurity and a second impurity; and a third epitaxial layer on the second epitaxial layer and including the first impurity, and in a horizontal sectional view, the second epitaxial layer includes a peripheral portion having a thickness in the first direction that increases along the second direction.

公开(公告)号：US11664453B2

公开(公告)日：2023-05-30

申请号：US17192301

申请日：2021-03-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaemun Kim ,  Dahye Kim ,  Jinbum Kim ,  Gyeom Kim ,  Dohee Kim ,  Dongwoo Kim ,  Seunghun Lee

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/04

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L29/41791 ,  H01L29/6681 ,  H01L29/66818 ,  H01L29/045

Abstract: A semiconductor device includes a substrate including a fin-type active region, the fin-type active region extending in a first direction; a plurality of channel layers on the fin-type active region, the plurality of channel layers including an uppermost channel layer, a lowermost channel layer, and an intermediate channel layer isolated from direct contact with each other in a direction perpendicular to an upper surface of the substrate; a gate electrode surrounding the plurality of channel layers and extending in a second direction intersecting the first direction; a gate insulating film between the plurality of channel layers and the gate electrode; and source/drain regions electrically connected to the plurality of channel layers. In a cross section taken in the second direction, the uppermost channel layer has a width greater than a width of the intermediate channel layer.

公开(公告)号：US11626401B2

公开(公告)日：2023-04-11

申请号：US16991530

申请日：2020-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaemun Kim ,  Gyeom Kim ,  Dahye Kim ,  Jinbum Kim ,  Kyungin Choi ,  Ilgyou Shin ,  Seunghun Lee

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/02

Abstract: An integrated circuit device includes: a fin-type active area protruding from a substrate, extending in a first direction parallel to an upper surface of the substrate, and including a first semiconductor material; an isolation layer arranged on the substrate and covering a lower portion of a sidewall of the fin-type active area, the isolation layer including an insulation liner conformally arranged on the lower portion of the sidewall of the fin-type active area, and an insulation filling layer on the insulation liner; a capping layer surrounding an upper surface and the sidewall of the fin-type active area, including a second semiconductor material different from the first semiconductor material, and with the capping layer having an upper surface, a sidewall, and a facet surface between the upper surface and the sidewall; and a gate structure arranged on the capping layer and extending in a second direction perpendicular to the first direction.

公开(公告)号：US20220059654A1

公开(公告)日：2022-02-24

申请号：US17207690

申请日：2021-03-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinbum Kim ,  Seokhoon Kim ,  Kwanheum Lee ,  Choeun Lee ,  Sujin Jung

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/167 ,  H01L29/786 ,  H01L29/06 ,  H01L29/66

Abstract: A semiconductor device includes a channel, a first source/drain structure on a first side surface of the channel, a second source/drain structure on a second side surface of the channel, a gate structure surrounding the channel, an inner spacer layer on a side surface of the gate structure, and an outer spacer layer on an outer surface of the inner spacer layer. The first source/drain structure includes a first source/drain layer on the channel and a second source/drain layer on the first source/drain layer, and on a plane of the semiconductor device that passes through the channel, at least one of a first boundary line of the first source/drain layer in contact with the second source/drain layer and a second boundary line of the first source/drain layer in contact with the channel may be convex, extending toward the channel.

公开(公告)号：US11094832B2

公开(公告)日：2021-08-17

申请号：US16744642

申请日：2020-01-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dahye Kim ,  Dongchan Suh ,  Jinbum Kim

IPC: H01L29/786 ,  H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66

Abstract: A semiconductor device includes an active region extending on a substrate in a first direction and including an impurity region, a plurality of channel layers vertically spaced apart from each other on the active region, a gate structure extending on the substrate in a second direction to intersect the active region and the plurality of channel layers, and surrounding the plurality of channel layers, a source/drain region disposed on the active region on at least one side of the gate structure and in contact with the plurality of channel layers, a barrier layer including a first barrier layer spaced apart from an upper surface of the active region and being disposed in the active region, and second barrier layers respectively disposed below the plurality of channel layers, and a contact plug connected to the source/drain region.

公开(公告)号：US20250092522A1

公开(公告)日：2025-03-20

申请号：US18669753

申请日：2024-05-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinbum Kim

IPC: C23C16/46 ,  C23C16/44 ,  C23C16/455 ,  C23C16/48 ,  C23C16/52 ,  H01L21/02

Abstract: A semiconductor processing apparatus includes a support configured to support a wafer, a chamber including an upper dome and a lower dome, a facility cover that at least partially surrounds the chamber, a pre-heating unit that is below the support and is configured to heat the wafer, an upper lamp that is on the chamber and is configured to heat the wafer, a first process gas supply unit configured to supply a first process gas to the chamber, a second process gas supply unit configured to supply a second process gas to the chamber, a valve that is between the second process gas supply unit and the chamber, a pump that is connected to the chamber and is configured to discharge gas from the chamber, and a control unit, where the pre-heating unit includes a first lamp that is different from the upper lamp.