-
公开(公告)号:US20250142804A1
公开(公告)日:2025-05-01
申请号:US18734052
申请日:2024-06-05
Applicant: Samsung Electronics Co., Ltd.
Inventor: Iljae SHIN , Kiseok LEE , Seokhan PARK , Sungmin PARK , Dongjun LEE
IPC: H10B12/00
Abstract: A semiconductor device includes gate electrodes extending in a first horizontal direction on a memory cell region and stacked and spaced apart from each other in a vertical direction, back-gate electrodes extending between the gate electrodes in the first horizontal direction and stacked and spaced apart from each other in the vertical direction, vertical conductive patterns extending in the vertical direction and spaced apart from each other in the first horizontal direction on the memory cell region, active layers between the gate electrodes and the back-gate electrodes, extending in a second horizontal direction intersecting with the first horizontal direction, and electrically connected to the vertical conductive patterns on the memory cell region, and a through-plug extending in the vertical direction and in contact with side surfaces of the back-gate electrodes.
-
公开(公告)号:US20240365535A1
公开(公告)日:2024-10-31
申请号:US18397014
申请日:2023-12-27
Applicant: SAMSUNG ELECTRONICS CO, LTD.
Inventor: Jongmin KIM , Kiseok LEE , Bongsoo KIM , Chan-Sic YOON
IPC: H10B12/00
CPC classification number: H10B12/488 , H10B12/315 , H10B12/482 , H10B12/485
Abstract: A semiconductor device includes a first active pattern including a first edge portion and a second edge portion, which are spaced apart from each other in a first direction; a first word line between the first edge portion of the first active pattern and the second edge portion of the first active pattern and extending in a second direction that crosses the first direction; a bit line on the first edge portion of the first active pattern and extending in a third direction that crosses the first direction and the second direction; and a storage node contact on the second edge portion of the first active pattern, wherein a top surface of the first edge portion is at a level higher than a top surface of the second edge portion.
-
公开(公告)号:US20240315005A1
公开(公告)日:2024-09-19
申请号:US18388266
申请日:2023-11-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Kiseok LEE , Sangjae PARK , Huijung KIM , Taejin PARK , Chansic YOON , Myeongdong LEE
IPC: H10B12/00
CPC classification number: H10B12/315 , H10B12/0335 , H10B12/482
Abstract: A semiconductor device includes an active pattern array including active patterns on a substrate; a first contact structure on a central portion of each active pattern; a bit line structure on the first contact structure; a second contact structure on an end of each active pattern; a third contact structure on the second contact structure; and a capacitor electrically connected to the third contact structure, wherein the active pattern array includes active pattern rows spaced apart from each other in a second direction parallel the substrate, the active pattern rows include active patterns spaced apart from each other in a first direction parallel to the substrate, the active patterns extend in a third direction having an acute angle with the first/second directions, the active patterns in the rows are aligned in the first direction, and the second contact structure has a rectangular shape in a plan view.
-
公开(公告)号:US20240268129A1
公开(公告)日:2024-08-08
申请号:US18370940
申请日:2023-09-21
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Hongjun LEE , Keunnam KIM , Hui-Jung KIM , Seokhan PARK , Kiseok LEE , Moonyoung JEONG , Jay-Bok CHOI , Hyungeun CHOI , Jinwoo HAN
IPC: H10B80/00 , H01L23/00 , H01L25/00 , H01L25/065 , H01L25/18
CPC classification number: H10B80/00 , H01L24/08 , H01L24/80 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/08145 , H01L2224/80895 , H01L2224/80896 , H01L2225/06541 , H01L2924/1431 , H01L2924/1436
Abstract: Disclosed are semiconductor devices and their fabrication methods. The semiconductor device comprises a lower substrate, a lower dielectric structure on the lower substrate, a memory cell structure between the lower substrate and the lower dielectric structure, a lower bonding pad in the lower dielectric structure, an upper dielectric structure on the lower dielectric structure, an upper substrate on the upper dielectric structure, a transistor between the upper substrate and the upper dielectric structure, and an upper bonding pad in the upper dielectric structure. A top surface of the lower bonding pad is in contact with a bottom surface of the upper bonding pad. The lower bonding pad and the upper bonding pad overlap the memory cell structure.
-
公开(公告)号:US20240268102A1
公开(公告)日:2024-08-08
申请号:US18471583
申请日:2023-09-21
Applicant: Samsung Electronics Co., Ltd.
Inventor: Kiseok LEE , Seung-Bo KO , Jongmin KIM , Hui-Jung KIM , SangJae PARK , Taejin PARK , Chan-Sic YOON , Myeong-Dong LEE , Hongjun LEE , Minju KANG , Keunnam KIM
IPC: H10B12/00
CPC classification number: H10B12/485 , H10B12/482 , H10B12/488
Abstract: A semiconductor device includes first and second active patterns extending in a first direction and arranged in a second direction intersecting the first direction, each of the first and second active patterns including first and second edge portions spaced apart from each other in the first direction, a first storage node pad and a first storage node contact sequentially provided on the first edge portion of the first active pattern, and a second storage node pad and a second storage node contact sequentially provided on the second edge portion of the second active pattern. Each of the first and second storage node contacts includes a metal material.
-
公开(公告)号:US20230180456A1
公开(公告)日:2023-06-08
申请号:US18059492
申请日:2022-11-29
Applicant: Samsung Electronics Co., Ltd.
Inventor: Euichul JEONG , Kiseok LEE , Wonki ROH , Hyungeun CHOI
IPC: H10B12/00
CPC classification number: H01L27/10805 , H01L27/1085 , H01L27/10873 , H01L27/10885
Abstract: A semiconductor memory device including a transistor body extending in a first horizontal direction and including a first source/drain region, a single-crystal channel layer, and a second source/drain region sequentially arranged in the first horizontal direction, a gate electrode layer extending in a second horizontal direction orthogonal to the first horizontal direction and covering upper and lower surfaces of the single-crystal channel layer, a bit line connected to the first source/drain region, extending in a vertical direction, and having a first width in the second horizontal direction, a spacer covering upper and lower surfaces of the first source/drain region and having a second width greater than the first width, and a cell capacitor on a side opposite to the bit line with respect to the transistor body in the first horizontal direction and including lower and upper electrode layers and a capacitor dielectric layer therebetween may be provided.
-
公开(公告)号:US20230055499A1
公开(公告)日:2023-02-23
申请号:US17805706
申请日:2022-06-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Kiseok LEE , Keunnam KIM , Hui-Jung KIM , Wonsok LEE , Min Hee CHO
IPC: H01L27/11582 , H01L27/11556 , H01L27/11519 , H01L27/11526 , H01L27/11565 , H01L27/11573
Abstract: A semiconductor memory device may be provided. The semiconductor memory device may include a bit line, a channel pattern on the bit line, the channel pattern including a horizontal channel portion, which is provided on the bit line, and a vertical channel portion, which is vertically extended from the horizontal channel portion, a word line provided on the channel pattern to cross the bit line, the word line including a horizontal portion, which is provided on the horizontal channel portion, and a vertical portion, which is vertically extended from the horizontal portion to face the vertical channel portion, and a gate insulating pattern provided between the channel pattern and the word line.
-
公开(公告)号:US20230044856A1
公开(公告)日:2023-02-09
申请号:US17873242
申请日:2022-07-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Taejin PARK , Kiseok LEE , Hui-Jung KIM , Yoosang HWANG
IPC: H01L29/423 , H01L21/768 , H01L21/762 , H01L21/02 , G11C5/06
Abstract: A semiconductor memory device including a substrate including an active pattern that includes a first source/drain region and a second source/drain region; an insulating layer on the substrate; a line structure on the insulating layer and extending in a first direction to cross the active pattern, the line structure penetrating the insulating layer on the first source/drain region and including a bit line electrically connected to the first source/drain region; and a contact spaced apart from the line structure and electrically connected to the second source/drain region, wherein the bit line includes a first portion vertically overlapped with the first source/drain region; and a second portion vertically overlapped with the insulating layer, and wherein a lowermost level of a top surface of the first portion of the bit line is at a level lower than a lowermost level of a top surface of the second portion of the bit line.
-
公开(公告)号:US20220102352A1
公开(公告)日:2022-03-31
申请号:US17241860
申请日:2021-04-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Kiseok LEE , Kyunghwan LEE , Dongoh KIM , Yongseok KIM , Hui-jung KIM , Min Hee CHO
IPC: H01L27/108
Abstract: A semiconductor memory device includes a bit line extending in a first direction, a channel pattern on the bit line, the channel pattern including first and second vertical portions facing each other and a horizontal portion connecting the first and second vertical portions, first and second word lines provided on the horizontal portion and between the first and second vertical portions and extended in a second direction crossing the bit line, and a gate insulating pattern provided between the first word line and the channel pattern and between the second word line and the channel pattern.
-
公开(公告)号:US20210408008A1
公开(公告)日:2021-12-30
申请号:US17471824
申请日:2021-09-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Kiseok LEE , Chan-Sic YOON , Augustin HONG , Keunnam KIM , Dongoh KIM , Bong-Soo KIM , Jemin PARK , Hoin LEE , Sungho JANG , Kiwook JUNG , Yoosang HWANG
IPC: H01L27/108 , H01L27/24
Abstract: A method of manufacturing a semiconductor memory device and a semiconductor memory device, the method including providing a substrate that includes a cell array region and a peripheral circuit region; forming a mask pattern that covers the cell array region and exposes the peripheral circuit region; growing a semiconductor layer on the peripheral circuit region exposed by the mask pattern such that the semiconductor layer has a different lattice constant from the substrate; forming a buffer layer that covers the cell array region and exposes the semiconductor layer; forming a conductive layer that covers the buffer layer and the semiconductor layer; and patterning the conductive layer to form conductive lines on the cell array region and to form a gate electrode on the peripheral circuit region.
-
-
-
-
-
-
-
-
-