公开(公告)号：KR20200141231A

公开(公告)日：2020-12-18

申请号：KR20190067959

申请日：2019-06-10

Applicant: SAMSUNG ELECTRONICS CO LTD

Inventor： DOIL KANG ,  MINSOO KIM ,  JIWOO LEE

IPC: H04M1/02 ,  H05K1/14 ,  H05K9/00

Abstract: 다양한실시예들에따르면, 슬라이드(slide) 타입(type)의전자장치는메인바디(main body); 상기메인바디와결합되고회전운동이가능한가이드레일; 상기메인바디와결합되고상기가이드레일의회전운동을제어하는구동장치; 상기메인바디와결합되는가이드구조체; 슬라이드바디(slide body); 및상기슬라이드바디와결합되는연결구조체(connector structure)를포함하고, 상기연결구조체는, 상기회전운동에따라직선이동하도록상기가이드레일과결합되고, 상기연결구조체의직선이동에따라상기슬라이드바디는지정된영역에서유동적으로배치되고, 상기연결구조체의일 면과상기가이드구조체의일 면은전기적연결을형성하도록구성될수 있다.

公开(公告)号：KR20200134670A

公开(公告)日：2020-12-02

申请号：KR20190060444

申请日：2019-05-23

Applicant: SAMSUNG ELECTRONICS CO LTD

Inventor： JAEHONG JUNG ,  MINSOO KIM ,  SANGMIN LEE ,  JIWOO LEE

IPC: H04M1/02

Abstract: 전자장치가개시된다. 다양한실시예에따른전자장치는, 폴더블하우징으로서, 폴더블하우징을접힘(folding) 또는펼침(unfolding)상태로전환가능한힌지구조물, 힌지구조물에연결되며, 제1 방향으로향하는제1 면, 상기제1 방향과반대인제2 방향으로향하는제2 면을포함하는제1 하우징구조와, 힌지구조물에연결되며, 제3 방향으로향하는제3 면, 상기제3 방향과반대인제4 방향으로향하는제4 면을포함하며, 상기힌지구조를축으로하여상기제1 하우징구조와접하는제2 하우징구조를포함하는폴더블하우징, 제1 면으로부터제3 면으로연장되어제1 면및 제3 면을형성하는제1 디스플레이, 제4 면의적어도일부분을형성하는제2 디스플레이와, 제2 면또는제4 면중 적어도하나에배치되는적어도하나의음향입력장치를포함하는것을특징으로한다.

公开(公告)号：KR20200140544A

公开(公告)日：2020-12-16

申请号：KR20190067303

申请日：2019-06-07

Applicant: SAMSUNG ELECTRONICS CO LTD

Inventor： SUNGWON BAN ,  MINSOO KIM ,  HOYEON KIM ,  MIN SAKONG ,  HYEONTAE CHO ,  SUNGJUN KIM

IPC: H01Q1/38 ,  H01Q1/24 ,  H01R12/57

Abstract: 다양한실시예들에따르면, 전자장치(electronic device)는안테나(antenna) 및제1 PCB(print circuit board)를포함하는제1 구조체(body), 상기안테나는상기제1 PCB에배치되고, RF(radio frequency) 모듈및 제2 PCB를포함하는제2 구조체(body), 상기 RF 모듈은상기제2 PCB에배치되고, 상기제1 구조체를제1 상태에서제2 상태로이동시키는프레임(slide frame); 및상기제1 구조체와상기제2 구조체를전기적으로(electrically) 연결시키는연결구조를포함할수 있다. 상기연결구조는, 상기제1 PCB 상에배치되는적어도하나의안테나연결단자; 및상기제2 PCB 상에배치되는적어도둘 이상의 RF 연결단자들을포함하고, 상기적어도둘 이상의 RF 연결단자들은제1 RF 연결단자및 제2 RF 연결단자를포함하고, 상기제1 구조체는, 상기제1 상태에서상기연결구조를통해상기제1 RF 연결단자와전기적으로연결되고, 상기제2 상태에서상기연결구조를통해상기제2 RF 연결단자와전기적으로연결되고, 상기제2 PCB는상기제1 RF 연결단자에대한제1 RF 튜닝회로(tuning circuit) 및상기제2 RF 연결단자에대한제2 RF 튜닝회로를포함할수 있다.

公开(公告)号：US20190303226A1

公开(公告)日：2019-10-03

申请号：US16218720

申请日：2018-12-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MINSU KIM ,  JISEOK KANG ,  MINSOO KIM ,  BYUNGJIK KIM ,  WONJAE SHIN ,  DONGHOON LEE ,  YEONHWA LEE ,  HO-YOUNG LEE ,  YOUJIN JANG ,  INSU CHOI

IPC: G06F11/07 ,  G06F12/0804 ,  G06F12/02

Abstract: A semiconductor memory module may include a random access memory, a nonvolatile memory, a buffer memory, and a controller configured to execute a reading operation on the buffer memory in response to an activation of a control signal. The controller may be further configured to execute a flush operation of storing first data, which are stored in the random access memory, in the nonvolatile memory, according to a result of the reading operation.

公开(公告)号：US20230230946A1

公开(公告)日：2023-07-20

申请号：US17939127

申请日：2022-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seongyo KIM ,  UN-BYOUNG KANG ,  MINSOO KIM ,  SANG-SICK PARK ,  Seungyoon JUNG

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/09 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/08 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/81203 ,  H01L24/81 ,  H01L2924/3511 ,  H01L2924/182 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2225/06589 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/1703 ,  H01L2224/17055 ,  H01L2224/17104 ,  H01L2224/17179 ,  H01L2224/17132 ,  H01L2224/16012 ,  H01L2224/16055 ,  H01L2224/16059 ,  H01L2224/16104 ,  H01L2224/0801 ,  H01L2224/08056 ,  H01L2224/08055 ,  H01L2224/0903 ,  H01L2224/09179 ,  H01L2224/09132 ,  H01L2224/73204

Abstract: A semiconductor package comprises a first die having a central region and a peripheral region that surrounds the central region; a plurality of through electrodes that penetrate the first die; a plurality of first pads at a top surface of the first die and coupled to the through electrodes; a second die on the first die; a plurality of second pads at a bottom surface of the second die, the bottom surface of the second die facing the top surface of the first die; a plurality of connection terminals that connect the first pads to the second pads; and a dielectric layer that fills a space between the first die and the second die and surrounds the connection terminals. A first width of each of the first pads in the central region may be greater than a second width of each of the first pads in the peripheral region. Each of the connection terminals may include a convex portion at a lateral surface thereof, which protrudes beyond a lateral surface of a respective first pad and a lateral surface of a respective second pad. The convex portion may protrude in a direction away from a center of the first die. Protruding distances of the convex portions may increase in a direction from the center of the first die toward an outside of the first die.

公开(公告)号：US20250070072A1

公开(公告)日：2025-02-27

申请号：US18640576

申请日：2024-04-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seongyo KIM ,  MINSOO KIM ,  SANG-SICK PARK

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065

Abstract: A semiconductor package includes a first semiconductor die, a first under-fill layer on an upper surface of the first semiconductor die, a second under-fill layer on the first under-fill layer, a second semiconductor die provided on the second under-fill layer, and a mold layer on side surfaces of the second semiconductor die, the second under-fill layer, and the upper surface of the first semiconductor die. The first semiconductor die includes a first substrate, a first redistribution pattern on the first substrate, a first redistribution dielectric layer provided on the first redistribution pattern, and a first dam on the first redistribution dielectric layer and along an edge of the first substrate, and the first under-fill layer contacts a side surface of the first dam.