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    METHOD FOR REDUCING CURRENT CONSUMPTION, AND ELECTRONIC DEVICE
    3.
    发明申请
    METHOD FOR REDUCING CURRENT CONSUMPTION, AND ELECTRONIC DEVICE 审中-公开

    公开(公告)号：US20200293104A1

    公开(公告)日：2020-09-17

    申请号：US16086084

    申请日：2017-03-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seung Jin KIM ,  Ji Hun KIM ,  Gwang Hui LEE ,  Sung Jun LEE ,  Woo Jun JUNG ,  Min Jung KIM

    IPC: G06F1/3225 ,  G06F3/14 ,  G09G5/393 ,  G09G5/397

    Abstract: Various examples of the present invention relate to an electronic device comprising: a graphic buffer for storing graphic information received from an application; a frame buffer for storing the graphic information to be displayed on a display; and a processor, wherein the processor is configured to: store, in the graphic buffer, first graphic information received from a first layer; store, in the frame buffer, second graphic information received from a second layer; store, in the frame buffer, the first graphic information stored in the graphic buffer; and simultaneously display the first graphic information and the second graphic information, stored in the frame buffer, through the display functionally connected with the processor. In addition, other examples identifiable through the specification are possible.

    SEMICONDUCTOR DEVICE HAVING SUPPORTER PATTERN
    5.
    发明申请
    SEMICONDUCTOR DEVICE HAVING SUPPORTER PATTERN 审中-公开

    公开(公告)号：US20200303492A1

    公开(公告)日：2020-09-24

    申请号：US16556786

    申请日：2019-08-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seung Jin KIM ,  Sung Soo YIM

    IPC: H01L49/02 ,  H01L27/108

    Abstract: A method of manufacturing a semiconductor device includes sequentially stacking a mold layer and a supporter layer on a substrate, forming a plurality of capacitor holes passing through the mold layer and supporter layer, forming a plurality of lower electrodes filling the capacitor holes, forming a supporter mask pattern having a plurality of mask holes on the supporter layer and the lower electrodes, and forming a plurality of supporter holes by patterning the supporter layer. Each of the plurality of lower electrodes has a pillar shape, and each of the mask holes is between four adjacent lower electrodes and has a circular shape.

    PHASE LOCKED LOOP CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME
    6.
    发明公开
    PHASE LOCKED LOOP CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME 审中-公开

    公开(公告)号：US20240106441A1

    公开(公告)日：2024-03-28

    申请号：US18466438

    申请日：2023-09-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyung Min LEE ,  Gyu Sik KIM ,  Seung Jin KIM ,  Jae Hong JUNG

    IPC: H03L7/093 ,  G05F3/26 ,  H03L1/00 ,  H03L7/099

    CPC classification number: H03L7/093 ,  G05F3/262 ,  H03L1/00 ,  H03L7/0995

    Abstract: A phase locked loop circuit and a semiconductor device are provided. The phased locked loop circuit includes a reference current generator configured to generate a summed compensation current in which at least one of a process change, a temperature change or a power supply voltage change are compensated and output the summed compensation current as a reference current, a current digital-to-analog converter configured to convert the reference current into a control current in accordance with a digital code and a voltage control oscillator configured to generate a signal based on the control current, wherein the summed compensation current is based on weighted-averaging a first type compensation current and a second type compensation current in response to at least one of the process change, the temperature change or the power supply voltage change.

    SEMICONDUCTOR DEVICE HAVING SUPPORTER PATTERN
    7.
    发明公开
    SEMICONDUCTOR DEVICE HAVING SUPPORTER PATTERN 审中-公开

    公开(公告)号：US20240128310A1

    公开(公告)日：2024-04-18

    申请号：US18396302

    申请日：2023-12-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seung Jin KIM ,  Sung Soo YIM

    IPC: H01G4/38 ,  H10B12/00

    CPC classification number: H01L28/90 ,  H10B12/033 ,  H10B12/315

    Abstract: A method of manufacturing a semiconductor device includes sequentially stacking a mold layer and a supporter layer on a substrate, forming a plurality of capacitor holes passing through the mold layer and supporter layer, forming a plurality of lower electrodes filling the capacitor holes, forming a supporter mask pattern having a plurality of mask holes on the supporter layer and the lower electrodes, and forming a plurality of supporter holes by patterning the supporter layer. Each of the plurality of lower electrodes has a pillar shape, and each of the mask holes is between four adjacent lower electrodes and has a circular shape.

    SEMICONDUCTOR DEVICE HAVING SUPPORTER PATTERN
    8.
    发明申请
    SEMICONDUCTOR DEVICE HAVING SUPPORTER PATTERN 有权

    公开(公告)号：US20220020845A1

    公开(公告)日：2022-01-20

    申请号：US17489961

    申请日：2021-09-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seung Jin KIM ,  Sung Soo YIM

    IPC: H01L49/02 ,  H01L27/108

    Abstract: A method of manufacturing a semiconductor device includes sequentially stacking a mold layer and a supporter layer on a substrate, forming a plurality of capacitor holes passing through the mold layer and supporter layer, forming a plurality of lower electrodes filling the capacitor holes, forming a supporter mask pattern having a plurality of mask holes on the supporter layer and the lower electrodes, and forming a plurality of supporter holes by patterning the supporter layer. Each of the plurality of lower electrodes has a pillar shape, and each of the mask holes is between four adjacent lower electrodes and has a circular shape.

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