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公开(公告)号:US20220230912A1
公开(公告)日:2022-07-21
申请号:US17714546
申请日:2022-04-06
Applicant: Samsung Electronics Co., Ltd.
Inventor: Dowan KIM , Doohwan LEE , Seunghwan BAEK
IPC: H01L21/768 , H01L23/538 , H01L23/00 , H01L23/31
Abstract: A method of manufacturing a semiconductor package may include forming a first substrate including a redistribution layer, providing a second substrate including a semiconductor chip and an interconnection layer on the first substrate to connect the semiconductor chip to the redistribution layer, forming a first encapsulation layer covering the second substrate, and forming a via structure penetrating the first encapsulation layer. The forming the via structure may include forming a first via hole in the first encapsulation layer, forming a photosensitive material layer in the first via hole, exposing and developing the photosensitive material layer in the first via hole to form a second encapsulation layer having a second via hole, and filling the second via hole with a conductive material. A surface roughness of a sidewall of the first encapsulation layer may be greater than a surface roughness of a sidewall of the second encapsulation layer.
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公开(公告)号:US20210202303A1
公开(公告)日:2021-07-01
申请号:US16983298
申请日:2020-08-03
Applicant: Samsung Electronics Co., Ltd.
Inventor: Dowan KIM , Doohwan LEE , Seunghwan BAEK
IPC: H01L21/768 , H01L23/538 , H01L23/31 , H01L23/00
Abstract: A method of manufacturing a semiconductor package may include forming a first substrate including a redistribution layer, providing a second substrate including a semiconductor chip and an interconnection layer on the first substrate to connect the semiconductor chip to the redistribution layer, forming a first encapsulation layer covering the second substrate, and forming a via structure penetrating the first encapsulation layer. The forming the via structure may include forming a first via hole in the first encapsulation layer, forming a photosensitive material layer in the first via hole, exposing and developing the photosensitive material layer in the first via hole to form a second encapsulation layer having a second via hole, and filling the second via hole with a conductive material. A surface roughness of a sidewall of the first encapsulation layer may be greater than a surface roughness of a sidewall of the second encapsulation layer.
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