Semiconductor devices and methods for forming the same

    公开(公告)号:US10910398B2

    公开(公告)日:2021-02-02

    申请号:US16165426

    申请日:2018-10-19

    Abstract: A semiconductor device may include a cell gate conductive pattern in a cell array area that extends to a step area, a cell vertical structure in the cell array area that extends through the cell gate conductive pattern, a cell gate contact structure on the cell gate conductive pattern in the step area, a cell gate contact region in the cell gate conductive pattern and aligned with the cell gate contact structure, a first peripheral contact structure spaced apart from the cell gate conductive pattern, a second peripheral contact structure spaced apart from the first peripheral contact structure, a first peripheral contact region under the first peripheral contact structure, and a second peripheral contact region under the second peripheral contact structure. The cell gate contact region may include a first element and a remainder of the cell gate conductive pattern may not substantially include the first element.

    MEMORY SEMICONDUCTOR DEVICE AND METHOD OF OPERATING THE SAME
    7.
    发明申请
    MEMORY SEMICONDUCTOR DEVICE AND METHOD OF OPERATING THE SAME 审中-公开
    存储器半导体器件及其操作方法

    公开(公告)号:US20140133223A1

    公开(公告)日:2014-05-15

    申请号:US14159369

    申请日:2014-01-20

    CPC classification number: G11C16/3427 G11C16/0483 G11C16/26

    Abstract: In a read step or a program (write) verification step of a semiconductor memory device, read voltages different from one another are applied to a pair of word lines respectively disposed on both sides of a selected word line to suppress the enlargement of program distribution.

    Abstract translation: 在半导体存储器件的读取步骤或程序(写入)验证步骤中,彼此不同的读取电压被施加到分别设置在所选字线的两侧上的一对字线,以抑制程序分配的扩大。

    Semiconductor devices and methods for forming the same

    公开(公告)号:US12022653B2

    公开(公告)日:2024-06-25

    申请号:US17162526

    申请日:2021-01-29

    CPC classification number: H10B43/27 H10B43/40 H10B43/50

    Abstract: A semiconductor device may include a cell gate conductive pattern in a cell array area that extends to a step area, a cell vertical structure in the cell array area that extends through the cell gate conductive pattern, a cell gate contact structure on the cell gate conductive pattern in the step area, a cell gate contact region in the cell gate conductive pattern and aligned with the cell gate contact structure, a first peripheral contact structure spaced apart from the cell gate conductive pattern, a second peripheral contact structure spaced apart from the first peripheral contact structure, a first peripheral contact region under the first peripheral contact structure, and a second peripheral contact region under the second peripheral contact structure. The cell gate contact region may include a first element and a remainder of the cell gate conductive pattern may not substantially include the first element.

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