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    SEMICONDUCTOR DEVICE INCLUDING A GATE INSULATION PATTERN AND A GATE ELECTRODE PATTERN
    1.
    发明专利
    SEMICONDUCTOR DEVICE INCLUDING A GATE INSULATION PATTERN AND A GATE ELECTRODE PATTERN 未知

    公开(公告)号：SG10201804431UA

    公开(公告)日：2019-03-28

    申请号：SG10201804431U

    申请日：2018-05-24

    Applicant: SAMSUNG ELECTRONICS CO LTD

    Inventor： HYEOUNGWON SEO ,  WONSOK LEE ,  MIN HEE CHO ,  HYUN-SOOK BYUN

    IPC: H01L29/40 ,  H01L21/28 ,  H01L21/8242 ,  H01L27/108

    Abstract: A semiconductor device includes a substrate including an active region defined by a device isolation layer. A word line structure is in a trench formed in an upper portion of the substrate. The word line structure includes a gate insulation pattern covering an inner surface of the trench. A gate electrode pattern is on the gate insulation pattern. A first work function pattern is between the gate insulation pattern and the gate electrode pattern. A second work function pattern is on the first work function pattern and extends along a side surface of the gate electrode pattern. The first work function pattern has a top surface at a level below that of a bottom surface of the gate electrode pattern. The first work function pattern has a work function greater than that of the second work function pattern. FIG. 2

    Semiconductor Memory Devices
    2.
    发明专利
    Semiconductor Memory Devices 未知

    公开(公告)号：SG10201804042RA

    公开(公告)日：2019-03-28

    申请号：SG10201804042R

    申请日：2018-05-14

    Applicant: SAMSUNG ELECTRONICS CO LTD

    Inventor： HUI-JUNG KIM ,  MIN HEE CHO ,  BONG-SOO KIM ,  JUNSOO KIM ,  SATORU YAMADA ,  WONSOK LEE ,  YOOSANG HWANG

    IPC: H01L29/41 ,  H01L21/8242 ,  H01L27/108

    Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes an isolation layer in a first trench and a first gate electrode portion on the isolation layer. The semiconductor memory device includes a second gate electrode portion in a second trench. In some embodiments, the second gate electrode portion is wider, in a direction, than the first gate electrode portion. Moreover, in some embodiments, an upper region of the second trench is spaced apart from the first trench by a greater distance, in the direction, than a lower region of the second trench. Related methods of forming semiconductor memory devices are also provided. FIG. 1

    SEMICONDUCTOR MEMORY DEVICE
    4.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20220246180A1

    公开(公告)日：2022-08-04

    申请号：US17481583

    申请日：2021-09-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： WONSOK LEE ,  MIN TAE RYU ,  WOO BIN SONG ,  KISEOK LEE ,  MINSU LEE ,  MIN HEE CHO

    IPC: G11C5/06 ,  H01L29/06 ,  H01L27/108

    Abstract: A semiconductor memory includes a bit line extending in a first direction, first and second active patterns, which are alternately disposed in the first direction and on the bit line, and each of which includes a horizontal portion and a vertical portion, first word lines disposed on the horizontal portions of the first active patterns to cross the bit line, second word lines disposed on the horizontal portions of the second active patterns to cross the bit line, and an intermediate structure provided in a first gap region between the first and second word lines or in a second gap region between the vertical portions of the first and second active patterns. The first and second active patterns, which are adjacent to each other, may be disposed to be symmetric with respect to each other.

    SEMICONDUCTOR MEMORY DEVICE
    5.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20220013525A1

    公开(公告)日：2022-01-13

    申请号：US17172124

    申请日：2021-02-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： MIN HEE CHO ,  HYUNMOG PARK ,  WOO BIN SONG ,  MINSU LEE ,  WONSOK LEE

    IPC: H01L27/108

    Abstract: A semiconductor memory device is provided. The device may include a lower gate line provided on a substrate and extended in a first direction, an upper gate line vertically overlapped with the lower gate line and extended in the first direction, a first capacitor provided between the lower gate line and the upper gate line, a second capacitor provided between the lower gate line and the upper gate line and spaced apart from the first capacitor in the first direction, a lower semiconductor pattern provided to penetrate the lower gate line and connected to the first capacitor, an upper semiconductor pattern provided to penetrate the upper gate line and connected to the second capacitor, and a lower insulating pattern provided between the second capacitor and the lower gate line to cover the entire region of a bottom surface of the second capacitor.

    SEMICONDUCTOR DEVICE
    6.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20230328961A1

    公开(公告)日：2023-10-12

    申请号：US17987011

    申请日：2022-11-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： MIN HEE CHO ,  KISEOK LEE ,  WONSOK LEE

    IPC: H01L27/108

    CPC classification number: H01L27/10814 ,  H01L27/10897 ,  H01L27/10873

    Abstract: A semiconductor device includes a first conductive line that extends in a first horizontal direction, a plurality of semiconductor patterns on the first conductive line and spaced apart from each other in the first horizontal direction wherein each of the semiconductor patterns includes a first vertical part and a second vertical part that are opposite to each other in the first horizontal direction, a second conductive line that extends in a second horizontal direction between the first vertical part and the second vertical part of each of the semiconductor patterns, the second horizontal direction intersecting the first horizontal direction, a gate dielectric pattern between the first vertical part and the second vertical part and between the second vertical part and the second conductive line, and a blocking pattern between neighboring semiconductor patterns.

    SEMICONDUCTOR MEMORY DEVICE
    7.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20230187548A1

    公开(公告)日：2023-06-15

    申请号：US17976955

    申请日：2022-10-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： WONSOK LEE ,  MIN TAE RYU ,  SUNGWON YOO ,  KISEOK LEE ,  MIN HEE CHO

    IPC: H01L29/78 ,  G11C5/06 ,  H01L29/08 ,  H01L29/10 ,  H01L27/105

    CPC classification number: H01L29/7827 ,  G11C5/063 ,  H01L27/1052 ,  H01L29/0847 ,  H01L29/1033

    Abstract: A semiconductor memory device includes bit lines disposed on a substrate and extending in a first direction in parallel to each other, a hydrogen supply insulating layer including hydrogen and filling a space between the bit lines, a source pattern located on each of the bit lines and being in partial contact with the hydrogen supply insulating layer, a hydrogen diffusion barrier layer covering a top surface of the hydrogen supply insulating layer and being in contact with a side surface of the source pattern, a first channel pattern located on the source pattern, a first word line being adjacent to a side surface of the first channel pattern and crossing over the bit lines, and a landing pad on the first channel pattern.

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