公开(公告)号：US20220068835A1

公开(公告)日：2022-03-03

申请号：US17212035

申请日：2021-03-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongwan KIM ,  Kyong Hwan KOH ,  Juhyeon OH ,  Yongkwan LEE

IPC: H01L23/552 ,  H01L23/498 ,  H01L21/56

Abstract: A semiconductor package including a substrate including at least one ground pad and a ground pattern; a semiconductor chip on the substrate; and a shield layer on the substrate and covering the semiconductor chip, wherein the shield layer extends onto a bottom surface of the substrate and includes an opening region on the bottom surface of the substrate, a bottom surface of the at least one ground pad is at the bottom surface of the substrate, a side surface of the ground pattern is at a side surface of the substrate, and the shield layer on the bottom surface of the substrate is in contact with the bottom surface of the at least one ground pad and in contact with the side surface of the ground pattern.

公开(公告)号：US20240079342A1

公开(公告)日：2024-03-07

申请号：US18195429

申请日：2023-05-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taejun JEON ,  Junwoo PARK ,  Yongkwan LEE ,  Seung Hwan KIM ,  Jongwan KIM

IPC: H01L23/544 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10 ,  H10B80/00

CPC classification number: H01L23/544 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/5385 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H10B80/00 ,  H01L24/16 ,  H01L2223/54426 ,  H01L2224/16145 ,  H01L2224/16227

Abstract: A semiconductor package including: a first substrate; a first semiconductor chip and a second substrate horizontally spaced apart from each other on the first substrate; and a molding layer on the first substrate, the first semiconductor chip and the second substrate, wherein a thickness of the first semiconductor chip is greater than a thickness of the second substrate, wherein the molding layer exposes a top surface of the second substrate, and wherein the second substrate has fiducial marks exposed on the top surface of the second substrate.

公开(公告)号：US20230170310A1

公开(公告)日：2023-06-01

申请号：US18103584

申请日：2023-01-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongwan KIM ,  Kyong Hwan KOH ,  Juhyeon OH ,  Yongkwan LEE

IPC: H01L23/552 ,  H01L23/498 ,  H01L21/56

CPC classification number: H01L23/552 ,  H01L23/49838 ,  H01L21/568 ,  H01L23/49816 ,  H01L2224/16227 ,  H01L24/16

Abstract: A semiconductor package including a substrate including at least one ground pad and a ground pattern; a semiconductor chip on the substrate; and a shield layer on the substrate and covering the semiconductor chip, wherein the shield layer extends onto a bottom surface of the substrate and includes an opening region on the bottom surface of the substrate, a bottom surface of the at least one ground pad is at the bottom surface of the substrate, a side surface of the ground pattern is at a side surface of the substrate, and the shield layer on the bottom surface of the substrate is in contact with the bottom surface of the at least one ground pad and in contact with the side surface of the ground pattern.

公开(公告)号：US20230395482A1

公开(公告)日：2023-12-07

申请号：US18060812

申请日：2022-12-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungjoo KIM ,  Yongkwan LEE ,  Seung Hwan KIM ,  Jongwan KIM ,  Junwoo PARK ,  Taejun JEON ,  Junhyeung JO

IPC: H01L23/498 ,  H01L25/16 ,  H01G4/228 ,  H01L23/538

CPC classification number: H01L23/49838 ,  H01L25/16 ,  H01L25/162 ,  H01G4/228 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5389 ,  H01G4/08

Abstract: A semiconductor package including a dielectric layer on a substrate and having an opening that partially exposes a top surface of the substrate, a capacitor chip on the substrate and in the opening of the dielectric layer, connection terminals between the substrate and the capacitor chip and connecting the substrate and the capacitor chip to each other, dielectric patches on the substrate and in the opening of the dielectric layer, and an under-fill filling a space between the substrate and the capacitor chip may be provided. The space between the substrate and the capacitor chip includes a first region, a second region, and a third region between the first and second regions. The connection terminals are on the first region and the second region. The dielectric patches are on the third region.

公开(公告)号：US20220189835A1

公开(公告)日：2022-06-16

申请号：US17376883

申请日：2021-07-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choongbin YIM ,  Dongwook KIM ,  Hyunki KIM ,  Jongbo SHIM ,  Jihwang KIM ,  Sungkyu PARK ,  Yongkwan LEE ,  Byoungwook JANG

IPC: H01L23/12 ,  H01L23/538

Abstract: A semiconductor package including a first package substrate, a first semiconductor chip on the first package substrate, a first conductive connector on the first package substrate and laterally spaced apart from the first semiconductor chip, an interposer substrate on the first semiconductor chip and electrically connected to the first package substrate through the first conductive connector, the interposer substrate including a first portion overlapping the first semiconductor chip and a plurality of upper conductive pads in the first portion, a plurality of spacers on a lower surface of the first portion of the interposer substrate and positioned so as not to overlap the plurality of upper conductive pads in a plan view, and an insulating filler between the interposer substrate and the first package substrate may be provided.

公开(公告)号：US20130178016A1

公开(公告)日：2013-07-11

申请号：US13736551

申请日：2013-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choongbin YIM ,  Eunchul AHN ,  Taesung PARK ,  Hak-kyoon BYUN ,  Yongkwan LEE

IPC: H01L25/00

CPC classification number: H01L25/105 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/00011 ,  H01L2224/83

Abstract: Methods of fabricating a package-on-package device and package-on-package devices fabricated by the same may be provided. According to inventive concepts, a back-grinding of a semiconductor chip to a target thickness may be performed after the semiconductor chip is molded by a molding layer. Accordingly, the semiconductor chip is relatively thick while forming a molding layer, and thus less susceptible to a warpage phenomenon, which for instance may occur during the forming a molding layer. Thus, relatively thin package-on-package device, which is less susceptible to the warpage phenomenon, may be achieved.

Abstract translation: 可以提供制造封装封装器件和由其制造的封装封装器件的方法。 根据本发明的概念，可以在通过模制层模制半导体芯片之后进行半导体芯片到目标厚度的背面磨削。 因此，半导体芯片在形成模制层的同时相对较厚，因此较不容易发生翘曲现象，例如可能在形成模制层期间发生。 因此，可以实现较不易受翘曲现象影响的较薄的封装封装器件。

公开(公告)号：US20240096748A1

公开(公告)日：2024-03-21

申请号：US18453026

申请日：2023-08-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taejun JEON ,  Yongkwan LEE ,  Gyuhyeong KIM ,  Seunghwan KIM ,  Jongwan KIM ,  Junwoo PARK

IPC: H01L23/473 ,  H01L23/00

CPC classification number: H01L23/473 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16052 ,  H01L2224/16175 ,  H01L2224/16225 ,  H01L2224/32221 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/17151 ,  H01L2924/172 ,  H01L2924/177

Abstract: A chip protection device includes a protection frame extending around side surfaces of a semiconductor chip mounted on a substrate. The protection frame includes a plurality of side walls, each wall facing and spaced apart from a respective side surface of the semiconductor chip, and a plurality of upper walls, each upper wall extending inward from an upper portion of a respective side wall toward the semiconductor chip. A plurality of apertures are formed through the side walls and through which a fluid enters and exits. The protection frame defines an inner space in which the fluid can flow via the plurality of apertures. Heat from the side surfaces of the semiconductor chip is transferred to the fluid in the inner space.

公开(公告)号：US20230282533A1

公开(公告)日：2023-09-07

申请号：US18315558

申请日：2023-05-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyoung OH ,  Hyunggil BAEK ,  Seunghwan KIM ,  Jungjoo KIM ,  Jongho PARK ,  Yongkwan LEE

IPC: H01L23/16 ,  H01L25/065 ,  H01L23/498 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/16 ,  H01L25/0657 ,  H01L23/49811 ,  H01L23/3128 ,  H01L23/5389

Abstract: A semiconductor package is provided. The semiconductor package includes: a first package substrate; a first semiconductor chip on the first package substrate; an interposer substrate including a lower surface facing the first package substrate, an upper surface opposite to the lower surface, and an upper conductive pad in the upper surface of the interposer substrate; a first dam structure on the upper surface of the interposer substrate and extending along an edge of the upper conductive pad; a first molding layer in contact with the lower and upper surfaces of the interposer substrate and with an outer wall of the first dam structure; and a conductive connector in contact with an inner wall of the at least one first dam structure and with the upper conductive pad.

公开(公告)号：US20220093519A1

公开(公告)日：2022-03-24

申请号：US17306290

申请日：2021-05-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongho PARK ,  Seunghwan KIM ,  Junyoung OH ,  Yonghyun KIM ,  Yongkwan LEE ,  Junga LEE

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L25/10 ,  H01L23/31

Abstract: A semiconductor package includes a first package substrate; a first semiconductor chip on the first package substrate; a first conductive connector on the first package substrate; and an interposer including a central portion on the first semiconductor chip and an outer portion having the first conductive connector attached thereto. The central portion of the interposer includes a bottom surface defining a recess from a bottom surface of the outer portion of the interposer in a vertical direction that is perpendicular to a top surface of the first package substrate. A thickness in the vertical direction of the outer portion of the interposer is greater than a thickness in the vertical direction of the central portion of the interposer.

公开(公告)号：US20210202352A1

公开(公告)日：2021-07-01

申请号：US17203084

申请日：2021-03-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunki KIM ,  Sangsoo KIM ,  Seung Hwan KIM ,  Kyung Suk OH ,  Yongkwan LEE ,  Jongho LEE

IPC: H01L23/433 ,  H01L25/065 ,  H01L23/00 ,  H01L23/367 ,  H01L25/07

Abstract: Disclosed is a semiconductor package comprising a package substrate, a first semiconductor chip on the package substrate and including a first region and a second region, a second semiconductor chip on the first region, a heat radiation spacer on the second region, a third semiconductor chip supported by the second semiconductor chip and the heat radiation spacer, and a molding layer covering the first to third semiconductor chips and the heat radiation spacer.