公开(公告)号：US09244766B2

公开(公告)日：2016-01-26

申请号：US14034251

申请日：2013-09-23

Applicant: Seagate Technology LLC

Inventor： Ara Patapoutian ,  Bruce Douglas Buch ,  Ryan James Goss ,  Mark Allen Gaertner ,  Arvind Sridharan

IPC: G06F11/10

CPC classification number: G06F11/1048

Abstract: Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a memory has a plurality of solid-state non-volatile memory cells. A processing circuit is connected to the memory and configured to direct the execution of a plurality of read error recovery routines in response to at least one uncorrectable read error in a data set retrieved from the memory. The recovery routines are executed in a selected order based on an elapsed recovery time parameter for each of the recovery routines and an estimated probability of success of each of the recovery routines.

Abstract translation: 用于管理诸如闪存之类的存储器中的数据的方法和装置。 根据一些实施例，存储器具有多个固态非易失性存储单元。 处理电路连接到存储器并且被配置为响应于从存储器检索的数据集中的至少一个不可校正的读取错误来引导执行多个读取错误恢复例程。 基于每个恢复例程的经过恢复时间参数和每个恢复例程的估计的成功概率，以所选择的顺序执行恢复例程。

公开(公告)号：US09201728B2

公开(公告)日：2015-12-01

申请号：US14025327

申请日：2013-09-12

Applicant: Seagate Technology LLC

Inventor： Ara Patapoutian ,  Ryan James Goss ,  Mark Allen Gaertner ,  Bruce Douglas Buch ,  Arvind Sridharan

IPC: G06F11/10

CPC classification number: G06F11/1012

Abstract: Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, the apparatus has a solid-state non-volatile memory and a processing circuit configured to write data to a selected location of the memory. The data are arranged in the form of multi-bit code words each comprising a user data payload and associated parity data configured to correct one or more bit errors in the user data payload. The processing circuit adjusts at least a selected one of a size of the code words, a size of the user data payloads or a size of the parity data responsive to at least a selected one of an accumulated count of access operations upon the selected location or an error rate associated with the selected location.

Abstract translation: 用于管理诸如闪存之类的存储器中的数据的方法和装置。 根据一些实施例，该装置具有固态非易失性存储器和被配置为将数据写入存储器的选定位置的处理电路。 数据以多位码字的形式排列，每个码字包括用户数据有效载荷和被配置为校正用户数据有效载荷中的一个或多个位错误的相关联的奇偶校验数据。 所述处理电路至少根据所选择的位置的访问操作的累积计数中的至少一个来选择所述码字的大小，所述用户数据有效载荷的大小或所述奇偶校验数据的大小中的一个， 与所选位置相关联的错误率。

公开(公告)号：US20140269059A1

公开(公告)日：2014-09-18

申请号：US14287510

申请日：2014-05-27

Applicant: Seagate Technology LLC

Inventor： Arvind Sridharan ,  Ara Patapoutian

IPC: G11C16/34 ,  G11C29/00

CPC classification number: G11C16/3459 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/28 ,  G11C16/349 ,  G11C29/00

Abstract: Cells of a solid-state, non-volatile memory are assigned to one of a plurality of groups. Each group is defined by expected symbols stored in the cells in view of actual symbols read from the cells. Based on cell counts within the groups, it can be determined that a shift in a reference voltage will reduce a collective bit error rate of the cells. The shift can be applied to data access operations affecting the cells.

Abstract translation: 将固态非易失性存储器的单元分配给多个组中的一个。 鉴于从单元读取的实际符号，每个组由存储在单元中的预期符号定义。 基于组内的单元计数，可以确定参考电压的偏移将降低单元的集合误码率。 该移位可以应用于影响单元的数据访问操作。

公开(公告)号：US20150089278A1

公开(公告)日：2015-03-26

申请号：US14034251

申请日：2013-09-23

Applicant: Seagate Technology LLC

Inventor： Ara Patapoutian ,  Bruce Douglas Buch ,  Ryan James Goss ,  Mark Allen Gaertner ,  Arvind Sridharan

IPC: G06F11/10

CPC classification number: G06F11/1048

Abstract: Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a memory has a plurality of solid-state non-volatile memory cells. A processing circuit is connected to the memory and configured to direct the execution of a plurality of read error recovery routines in response to at least one uncorrectable read error in a data set retrieved from the memory. The recovery routines are executed in a selected order based on an elapsed recovery time parameter for each of the recovery routines and an estimated probability of success of each of the recovery routines.

Abstract translation: 用于管理诸如闪存之类的存储器中的数据的方法和装置。 根据一些实施例，存储器具有多个固态非易失性存储单元。 处理电路连接到存储器并且被配置为响应于从存储器检索的数据集中的至少一个不可校正的读取错误来引导执行多个读取错误恢复例程。 基于每个恢复例程的经过恢复时间参数和每个恢复例程的估计的成功概率，以所选择的顺序执行恢复例程。

公开(公告)号：US20150074487A1

公开(公告)日：2015-03-12

申请号：US14025327

申请日：2013-09-12

Applicant: Seagate Technology LLC

Inventor： Ara Patapoutian ,  Ryan James Goss ,  Mark Allen Gaertner ,  Bruce Douglas Buch ,  Arvind Sridharan

IPC: G06F11/10

CPC classification number: G06F11/1012

Abstract: Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, the apparatus has a solid-state non-volatile memory and a processing circuit configured to write data to a selected location of the memory. The data are arranged in the form of multi-bit code words each comprising a user data payload and associated parity data configured to correct one or more bit errors in the user data payload. The processing circuit adjusts at least a selected one of a size of the code words, a size of the user data payloads or a size of the parity data responsive to at least a selected one of an accumulated count of access operations upon the selected location or an error rate associated with the selected location.

Abstract translation: 用于管理诸如闪存之类的存储器中的数据的方法和装置。 根据一些实施例，该装置具有固态非易失性存储器和被配置为将数据写入存储器的选定位置的处理电路。 数据以多位码字的形式排列，每个码字包括用户数据有效载荷和被配置为校正用户数据有效载荷中的一个或多个位错误的相关联的奇偶校验数据。 所述处理电路至少根据所选择的位置的访问操作的累积计数中的至少一个来选择所述码字的大小，所述用户数据有效载荷的大小或所述奇偶校验数据的大小中的一个， 与所选位置相关联的错误率。

公开(公告)号：US09042169B2

公开(公告)日：2015-05-26

申请号：US14287510

申请日：2014-05-27

Applicant: Seagate Technology LLC

Inventor： Arvind Sridharan ,  Ara Patapoutian

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/06 ,  G11C16/28 ,  G11C29/00

CPC classification number: G11C16/3459 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/28 ,  G11C16/349 ,  G11C29/00

Abstract: Cells of a solid-state, non-volatile memory are assigned to one of a plurality of groups. Each group is defined by expected symbols stored in the cells in view of actual symbols read from the cells. Based on cell counts within the groups, it can be determined that a shift in a reference voltage will reduce a collective bit error rate of the cells. The shift can be applied to data access operations affecting the cells.

Abstract translation: 将固态非易失性存储器的单元分配给多个组中的一个。 鉴于从单元读取的实际符号，每个组由存储在单元中的预期符号定义。 基于组内的单元计数，可以确定参考电压的偏移将降低单元的集合误码率。 该移位可以应用于影响单元的数据访问操作。