公开(公告)号：EP0961435A3

公开(公告)日：2003-09-17

申请号：EP99108473.2

申请日：1999-04-30

Applicant: Siemens Information and Communication Networks Inc.

Inventor： Cole, Steven R.

IPC: H04J3/16 ,  H04Q11/04

CPC classification number: G11C7/1051 ,  G11C7/1036 ,  G11C7/1078 ,  H04J3/0626 ,  H04J3/1641

Abstract: A memory buffer apparatus (29) includes an extended shift register (32) and a memory (30). The extended shift register (32) shifts a plurality of serial bits to produce a multi-bit data word. The multi-bit data word has a predetermined length based on a delay interval that is a multiple of a serial bit period. The memory (30) stores the bit-slice of the multi-bit data word. The bit-slice has a length less than that of the multi-bit data word. An extended output shift register (34) can also be included in the apparatus (29). The extended output shift register (34) has a length greater than the stored bit-slice, and performs a parallel-to-serial conversion of the bit-slice output from the memory (30).

公开(公告)号：EP0952710A2

公开(公告)日：1999-10-27

申请号：EP99104371.2

申请日：1999-03-04

Applicant: Siemens Information and Communication Networks Inc.

Inventor： Manzardo, Marcel ,  Farooq, Abid ,  Cole, Steven R.

IPC: H04L12/64 ,  H04J3/16

CPC classification number: H04L12/6418 ,  H04J3/1623 ,  H04L2012/6427 ,  H04L2012/6448 ,  H04L2012/6459 ,  H04L2012/6475 ,  H04L2012/6481

Abstract: A telecommunications system (18) is provided that includes a first controller (20) and a second controller (22) coupled using a packet-switched network (32). The controllers provide a low cost means of coupling isochronous telecommunication devices. The first controller (20) receives one or more isochronous input channels from a common control shelf (24), such as a private branch exchange (PBX), over a circuit-switched network (27). The first controller (20) encapsulates an isochronous frames from the common control shelf (27) into a data frame that is transferrable over the packet-switched network (32). The second controller (22) is configured to receive the data frame and extract the isochronous frame, which is then transmitted to a peripheral shelf (26), such as a line trunk unit (LTU), using an isochronous circuit-switched network (38). The controllers contain identical functionality, permitting bi-directional transmission of data between the common control and peripheral shelves. Each controller includes multiplex/de-multiplex functions normally associated with isochronous telephony, as well as a packetize/de-packetize functions for transferring data over the packet-switched network (32). The arrival rate of the data packets is used for synchronizing the two controllers.

Abstract translation: 一种电信系统（18）设置确实包括第一控制器（20）和第二控制器（22）使用分组交换网络（32）耦合。 所述控制器提供耦合同步电信设备的低成本的装置。 第一控制器（20）接收来自一个公共控制搁板（24）的一个或多个同步输入通道：诸如专用小交换机（PBX），在电路交换网络（27）。 第一控制器（20）封装在从公共控制搁板（27）转换成数据帧的同步帧是可转移确实在分组交换网络（32）。 第二控制器（22）被配置为接收所述数据帧并提取同步帧，在所有其然后反式mitted到外设层架（26）：如线路中继线单元（LTU），采用在同步电路交换网络（38 ）。 控制器包含于相同的功能，允许所述公共控制和外设层架之间的数据的双向传输。 每个控制器包括通常与同步相关联的电话复用/解复用功能，以及用于通过分组交换网络（32）传递环的数据的分组化/去分组化的功能。 所述数据分组的到达速率用于同步两个控制器。

公开(公告)号：EP0952710A3

公开(公告)日：2002-04-17

申请号：EP99104371.2

申请日：1999-03-04

Applicant: Siemens Information and Communication Networks Inc.

Inventor： Manzardo, Marcel ,  Farooq, Abid ,  Cole, Steven R.

IPC: H04L12/64 ,  H04J3/16 ,  H04J3/06

CPC classification number: H04L12/6418 ,  H04J3/1623 ,  H04L2012/6427 ,  H04L2012/6448 ,  H04L2012/6459 ,  H04L2012/6475 ,  H04L2012/6481

Abstract: A telecommunications system (18) is provided that includes a first controller (20) and a second controller (22) coupled using a packet-switched network (32). The controllers provide a low cost means of coupling isochronous telecommunication devices. The first controller (20) receives one or more isochronous input channels from a common control shelf (24), such as a private branch exchange (PBX), over a circuit-switched network (27). The first controller (20) encapsulates an isochronous frames from the common control shelf (27) into a data frame that is transferrable over the packet-switched network (32). The second controller (22) is configured to receive the data frame and extract the isochronous frame, which is then transmitted to a peripheral shelf (26), such as a line trunk unit (LTU), using an isochronous circuit-switched network (38). The controllers contain identical functionality, permitting bi-directional transmission of data between the common control and peripheral shelves. Each controller includes multiplex/de-multiplex functions normally associated with isochronous telephony, as well as a packetize/de-packetize functions for transferring data over the packet-switched network (32). The arrival rate of the data packets is used for synchronizing the two controllers.

公开(公告)号：EP0977109A1

公开(公告)日：2000-02-02

申请号：EP99111776.3

申请日：1999-06-18

Applicant: Siemens Information and Communication Networks Inc.

Inventor： Cole, Steven R. ,  Baca, Russell T.

IPC: G06F1/12 ,  G06F5/06

CPC classification number: G06F5/06 ,  G06F1/12

Abstract: A synchronization circuit (30) includes three flip-flops responsive to a common clock signal (CLK2). The input to the first flip-flop (32) represents the least significant bit (LSB) of a counter (31) included within a first clock domain. The CLK2 signal originates from a second clock domain. The output of the first flip-flop is provided as input to the second flip-flop (34), and the second flip-flop output is provided as input to the third flip-flop (36). An exclusive-or (XOR) gate (38) generates a synchronization signal in response to outputs of the second and third flip-flops (34-36). The synchronization signal is usable within the second clock domain and activate for one period of CLK2 subsequent to every transition occurring on the LSB input. The active state of the synchronization signal indicates that a predefined set of data inputs is stable and valid. In this manner, a single unsynchronized input signal, i.e., the LSB input, can be used to synchronize the data inputs.

Abstract translation: 同步电路（30）包括三个触发器响应于一个共同的时钟信号（CLK2）。 输入到第一触发器（32）darstellt的计数器（31）的至少显著位（LSB）包括在第一时钟域内。 所述CLK2信号从第二时钟域起源。 所述第一触发器的输出作为输入被提供到所述第二触发器（34）和所述第二触发器的输出作为输入被提供到第三触发器（36）。 响应于所述第二和第三触发器（34-36）的输出的异或（XOR）（38）基因率的同步信号的栅极。 所述同步信号是第二时钟域内可用并激活CLK2的一个周期之后每过渡发生的对LSB输入。 同步信号的活动状态指示没有一组预定义的数据输入是稳定和有效的。 以这种方式，单个的非同步输入信号，即，LSB的输入，可被用来将数据输入同步。

公开(公告)号：EP0961435A2

公开(公告)日：1999-12-01

申请号：EP99108473.2

申请日：1999-04-30

Applicant: Siemens Information and Communication Networks Inc.

Inventor： Cole, Steven R.

IPC: H04J3/16

CPC classification number: G11C7/1051 ,  G11C7/1036 ,  G11C7/1078 ,  H04J3/0626 ,  H04J3/1641

Abstract: A memory buffer apparatus (29) includes an extended shift register (32) and a memory (30). The extended shift register (32) shifts a plurality of serial bits to produce a multi-bit data word. The multi-bit data word has a predetermined length based on a delay interval that is a multiple of a serial bit period. The memory (30) stores the bit-slice of the multi-bit data word. The bit-slice has a length less than that of the multi-bit data word. An extended output shift register (34) can also be included in the apparatus (29). The extended output shift register (34) has a length greater than the stored bit-slice, and performs a parallel-to-serial conversion of the bit-slice output from the memory (30).

Abstract translation: 存储器缓冲设备（29）包括在延长的移位寄存器（32）和存储器（30）。 扩展移位寄存器（32）串行移位的多元化，以产生多比特数据字。 多比特数据字具有基于延迟间隔做了预定长度为一个串行比特周期的倍数。 所述存储器（30）存储所述多比特数据字的位片。 所述位片具有比所述多位数据字的更小的长度。 因此延长的输出移位寄存器（34）可以被包括在所述装置（29）。 扩展输出移位寄存器（34）的长度比所存储的位片更大，并且执行从存储器（30）输出的位片的并行到串行转换。