公开(公告)号：US11264418B2

公开(公告)日：2022-03-01

申请号：US16167241

申请日：2018-10-22

Applicant: Stratio Inc.

Inventor： Jae Hyung Lee ,  Yeul Na ,  Youngsik Kim ,  Woo-Shik Jung

IPC: H01L27/146 ,  H01L31/113 ,  H01L31/18 ,  H04N5/378 ,  H04N5/361

Abstract: A device for sensing light includes a first semiconductor region doped with a dopant of a first type and a second semiconductor region doped with a dopant of a second type. The second semiconductor region is positioned above the first semiconductor region. The device includes a gate insulation layer; a gate, a source, and a drain. The second semiconductor region has a top surface that is positioned toward the gate insulation layer and a bottom surface that is positioned opposite to the top surface of the second semiconductor region. The second semiconductor region has an upper portion that includes the top surface of the second semiconductor region and a lower portion that includes the bottom surface of the second semiconductor region and is mutually exclusive with the upper portion. The first semiconductor region is in contact with both the upper portion and the lower portion of the second semiconductor region.

公开(公告)号：US10600640B2

公开(公告)日：2020-03-24

申请号：US15624603

申请日：2017-06-15

Applicant: Stratio, Inc.

Inventor： Woo-Shik Jung ,  Yeul Na ,  Youngsik Kim ,  Jae Hyung Lee ,  Jin Hyung Lee

IPC: H01L21/02 ,  H01L21/302 ,  H01L21/324 ,  H01L21/265 ,  H01L21/311 ,  H01L21/306

Abstract: Methods for reducing surface roughness of germanium are described herein. In some embodiments, the surface roughness is reduced by thermal oxidation of germanium. In some embodiments, the surface roughness is further reduced by controlling a rate of the thermal oxidation. In some embodiments, the surface roughness is reduced by thermal annealing.

公开(公告)号：US20170287706A1

公开(公告)日：2017-10-05

申请号：US15624603

申请日：2017-06-15

Applicant: Stratio, Inc.

Inventor： Woo-Shik Jung ,  Yeul Na ,  Youngsik Kim ,  Jae Hyung Lee ,  Jin Hyung Lee

IPC: H01L21/02 ,  H01L21/265 ,  H01L21/311

Abstract: Methods for reducing surface roughness of germanium are described herein. In some embodiments, the surface roughness is reduced by thermal oxidation of germanium. In some embodiments, the surface roughness is further reduced by controlling a rate of the thermal oxidation. In some embodiments, the surface roughness is reduced by thermal annealing.

公开(公告)号：US10109662B2

公开(公告)日：2018-10-23

申请号：US14967262

申请日：2015-12-11

Applicant: Stratio Inc.

Inventor： Jae Hyung Lee ,  Yeul Na ,  Youngsik Kim ,  Woo-Shik Jung

IPC: H01L27/146 ,  H01L31/113 ,  H04N5/378 ,  H01L31/18

Abstract: A device for sensing light includes a first semiconductor region doped with a dopant of a first type and a second semiconductor region doped with a dopant of a second type. The second semiconductor region is positioned above the first semiconductor region. The device includes a gate insulation layer; a gate, a source, and a drain. The second semiconductor region has a top surface that is positioned toward the gate insulation layer and a bottom surface that is positioned opposite to the top surface of the second semiconductor region. The second semiconductor region has an upper portion that includes the top surface of the second semiconductor region and a lower portion that includes the bottom surface of the second semiconductor region and is mutually exclusive with the upper portion. The first semiconductor region is in contact with both the upper portion and the lower portion of the second semiconductor region.

公开(公告)号：US09378950B1

公开(公告)日：2016-06-28

申请号：US15051362

申请日：2016-02-23

Applicant: Stratio, Inc. ,  Stratio

Inventor： Jae Hyung Lee ,  Youngsik Kim ,  Yeul Na ,  Woo-Shik Jung

IPC: H01L21/336 ,  H01L21/02 ,  H01L21/308

CPC classification number: H01L21/3081 ,  H01L21/02057 ,  H01L21/02082 ,  H01L21/02636 ,  H01L21/30604

Abstract: A method for removing nuclei formed during a selective epitaxial growth process includes epitaxially growing a first group of one or more semiconductor structures over a substrate with one or more mask layers. A second group of a plurality of semiconductor structures is formed on the one or more mask layers. The method also includes forming one or more protective layers over the first group of one or more semiconductor structures. At least a subset of the second group of the plurality of semiconductor structures is exposed from the one or more protective layers. The method further includes, subsequent to forming the one or more protective layers over the first group of one or more semiconductor structures, etching at least the subset of the second group of the plurality of semiconductor structures.

Abstract translation: 一种用于去除在选择性外延生长工艺过程中形成的核的方法包括用一个或多个掩模层在衬底上外延生长第一组一个或多个半导体结构。 在一个或多个掩模层上形成第二组多个半导体结构。 该方法还包括在一个或多个半导体结构的第一组上形成一个或多个保护层。 多个半导体结构的第二组的至少一个子集从一个或多个保护层露出。 该方法还包括：在一个或多个半导体结构的第一组上形成一个或多个保护层之后，至少蚀刻多个半导体结构的第二组的子集。

公开(公告)号：US20160099372A1

公开(公告)日：2016-04-07

申请号：US14967262

申请日：2015-12-11

Applicant: Stratio Inc.

Inventor： Jae Hyung Lee ,  Yeul Na ,  Youngsik Kim ,  Woo-Shik Jung

IPC: H01L31/113 ,  H01L31/18 ,  H01L27/146

CPC classification number: H01L31/1136 ,  H01L27/14616 ,  H01L31/1804 ,  H04N5/378

Abstract: A device for sensing light includes a first semiconductor region doped with a dopant of a first type and a second semiconductor region doped with a dopant of a second type. The second semiconductor region is positioned above the first semiconductor region. The device includes a gate insulation layer; a gate, a source, and a drain. The second semiconductor region has a top surface that is positioned toward the gate insulation layer and a bottom surface that is positioned opposite to the top surface of the second semiconductor region. The second semiconductor region has an upper portion that includes the top surface of the second semiconductor region and a lower portion that includes the bottom surface of the second semiconductor region and is mutually exclusive with the upper portion. The first semiconductor region is in contact with both the upper portion and the lower portion of the second semiconductor region.

Abstract translation: 用于感测光的装置包括掺杂有第一类型的掺杂剂的第一半导体区域和掺杂有第二类型的掺杂剂的第二半导体区域。 第二半导体区域位于第一半导体区域的上方。 该器件包括栅绝缘层; 一个门，一个源头和一个排水沟。 第二半导体区域具有朝向栅极绝缘层定位的顶表面和与第二半导体区域的顶表面相对定位的底表面。 第二半导体区域具有包括第二半导体区域的顶表面的上部和包括第二半导体区域的底表面并与上部相互排斥的下部。 第一半导体区域与第二半导体区域的上部和下部部分接触。