公开(公告)号：US09626266B1

公开(公告)日：2017-04-18

申请号：US14671469

申请日：2015-03-27

Applicant: Synchronoss Technologies, Inc.

Inventor： Eoin Byrne ,  Dan Costelloe

IPC: G06F11/00 ,  G06F11/26

CPC classification number: G06F11/261 ,  G06F11/3664

Abstract: Embodiments of the present invention relate to an error simulator for a test platform. The test platform includes a test process, a system under test (SUT), the error simulator and at least one downstream system. The error simulator is a transparent proxy that intercepts traffic from/to the SUT. The error simulator forwards only “success” commands from the SUT to the downstream system(s) and forwards actual responses from the downstream system(s) to the SUT. However, when the error simulator receives a “failure” command from the SUT, the error simulator automatically returns a corresponding error message that is obtained from preprogrammed failure information to the SUT. The preprogrammed failure information details one or more “failure” commands and corresponding error messages, and is received from the test process by the error simulator either prior to the start of testing or immediately preceding a failure during a test.