公开(公告)号：US11996714B2

公开(公告)日：2024-05-28

申请号：US17558100

申请日：2021-12-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mustapha El Markhi ,  Alejandro Vera ,  Rohit Bhan

IPC: H02J7/00 ,  G01R31/36 ,  H02J7/02

CPC classification number: H02J7/00304 ,  G01R31/36 ,  H02J7/00 ,  H02J7/00712 ,  H02J7/00714 ,  H02J7/007192 ,  H02J7/02 ,  H02J7/00034 ,  H02J2207/20

Abstract: A battery charger includes a battery power regulator configured to set a charge signal provided to a battery based on a charge control signal and charge enable signal. The battery charger also includes a controller configured to provide the charge control signal to the battery power regulator. The controller is also configured to temporarily de-assert the charge enable signal for a predetermined amount of time in response to determining that a change is needed in the charge control signal. The controller is further configured to re-assert the charge enable signal after the predetermined amount of time.

公开(公告)号：US11695283B2

公开(公告)日：2023-07-04

申请号：US16277548

申请日：2019-02-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mustapha El Markhi ,  Alejandro Vera ,  Tonmoy Roy ,  Rohit Bhan

IPC: H02J7/00

CPC classification number: H02J7/0031 ,  H02J7/00 ,  H02J7/00302 ,  H02J7/00304

Abstract: Aspects of the disclosure provide for a circuit. In at least some examples, the circuit includes a logic circuit, a first comparator, a second comparator, and an AND logic circuit. The logic circuit has an output and the first comparator has a first input coupled to an input voltage (VIN) pin, a second input configured to receive a Vin under voltage lockout (VINUVLO) threshold value, and an output. The second comparator has a first input coupled to a power middle (PMID) pin, a second input coupled to a battery pin, and an output and the AND logic circuit has a first input coupled to the output of the logic circuit, a second input coupled to the output of the first comparator, a third input coupled to the output of the second comparator, and an output coupled to an input of a field-effect transistor (FET) control circuit.

公开(公告)号：US11239680B2

公开(公告)日：2022-02-01

申请号：US16354962

申请日：2019-03-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mustapha El Markhi ,  Alejandro Vera ,  Rohit Bhan

IPC: H02J7/00 ,  H02J7/02 ,  G01R31/36

Abstract: A battery charger includes a battery power regulator configured to set a charge signal provided to a battery based on a charge control signal and charge enable signal. The battery charger also includes a controller configured to provide the charge control signal to the battery power regulator. The controller is also configured to temporarily de-assert the charge enable signal for a predetermined amount of time in response to determining that a change is needed in the charge control signal. The controller is further configured to re-assert the charge enable signal after the predetermined amount of time.

公开(公告)号：US20220115889A1

公开(公告)日：2022-04-14

申请号：US17558100

申请日：2021-12-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mustapha El Markhi ,  Alejandro Vera ,  Rohit Bhan

IPC: H02J7/00 ,  G01R31/36 ,  H02J7/02

Abstract: A battery charger includes a battery power regulator configured to set a charge signal provided to a battery based on a charge control signal and charge enable signal. The battery charger also includes a controller configured to provide the charge control signal to the battery power regulator. The controller is also configured to temporarily de-assert the charge enable signal for a predetermined amount of time in response to determining that a change is needed in the charge control signal. The controller is further configured to re-assert the charge enable signal after the predetermined amount of time.

公开(公告)号：US10291163B2

公开(公告)日：2019-05-14

申请号：US15142219

申请日：2016-04-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Alejandro Vera ,  Shyamsunder Balasubramanian ,  Toshio Yamanaka ,  Toru Tanaka

IPC: H02P8/12 ,  G05F1/595

Abstract: A voltage regulator includes an output transistor, an error amplifier coupled to the output transistor, a cascode transistor coupled to the output transistor in series, and a cascode bias circuit coupled to the cascode transistor and the output transistor. The output transistor is configured to generate an output signal at a first voltage. The error amplifier is configured to receive a reference signal. The cascode bias circuit is configured to bias the cascode transistor such that, in response to a drain-to-source short circuit of the output transistor, the cascode transistor generates the output signal at the first voltage.