公开(公告)号：US20250066526A1

公开(公告)日：2025-02-27

申请号：US18942875

申请日：2024-11-11

Applicant: Texas Instruments Incorporated

Inventor： Nazila Dadvand ,  Benjamin Stassen Cook ,  Archana Venugopal ,  Luigi Colombo

IPC: C08F292/00 ,  C08F8/42 ,  C08J5/00 ,  C08K3/04 ,  C08K3/08 ,  C08K7/00 ,  C08L25/06 ,  C08L33/12 ,  G03F1/78

Abstract: A method of forming a composite material includes photo-initiating a polymerization of a monomer in a pattern of interconnected units to form a polymer microlattice. Unpolymerized monomer is removed from the polymer microlattice. The polymer microlattice is coated with a metal. The metal-coated polymer microlattice is dispersed in a polymer matrix.

公开(公告)号：US20230378023A1

公开(公告)日：2023-11-23

申请号：US17952111

申请日：2022-09-23

Applicant: Texas Instruments Incorporated

Inventor： Vinod Rai ,  Archana Venugopal ,  Blake Travis

IPC: H01L23/42 ,  H01L23/522 ,  H01L23/485 ,  H01L21/66

CPC classification number: H01L23/42 ,  H01L23/5228 ,  H01L23/485 ,  H01L22/12

Abstract: An electronic device includes a package structure, conductive leads partially exposed outside the package structure, and a semiconductor die having a semiconductor layer and a multilevel metallization structure, where the semiconductor die is enclosed by the package structure and the multilevel metallization structure includes a heater resistor, a sense resistor, and conductive metal features electrically coupled to respective terminals of the heater resistor and the sense resistor, with the conductive metal features electrically coupled to respective ones of the conductive leads.

公开(公告)号：US20230307312A1

公开(公告)日：2023-09-28

申请号：US18143446

申请日：2023-05-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Benjamin Stassen Cook ,  Archana Venugopal ,  Luigi Colombo ,  Robert Reid Doering

IPC: H01L23/367 ,  H01L23/373 ,  H01L21/48

CPC classification number: H01L23/3677 ,  H01L23/3733 ,  H01L21/4882 ,  H01L23/3731 ,  H01L23/3736

Abstract: An integrated circuit has a substrate and an interconnect region disposed on the substrate. The interconnect region includes a plurality of interconnect levels. Each interconnect level includes interconnects in dielectric material. The integrated circuit includes a thermal via in the interconnect region. The thermal via extends vertically in at least one of the interconnect levels in the interconnect region. The thermal via includes a cohered nanoparticle film in which adjacent nanoparticles are cohered to each other. The thermal via has a thermal conductivity higher than dielectric material touching the thermal via. The cohered nanoparticle film is formed by a method which includes an additive process.

公开(公告)号：US20230200238A1

公开(公告)日：2023-06-22

申请号：US17836731

申请日：2022-06-09

Applicant: Texas Instruments Incorporated

Inventor： Archana Venugopal ,  Jingjing Chen

IPC: H01L35/30 ,  H01L35/24 ,  H01L35/32

CPC classification number: H01L35/30 ,  H01L35/24 ,  H01L35/32

Abstract: A microelectronic device including a substrate having a semiconductor material containing an embedded thermoelectric cooler with thermally anisotropic mesas between the cold terminal and the hot terminal of the embedded thermoelectric cooler adjacent to a heat source; the adjacent embedded thermoelectric cooler providing a temperature reduction for the heat source resulting in increased safe operating area (SOA) for the microelectronic device. The thermally anisotropic mesas are formed in parallel with deep trenches used as isolation in the microelectronic device.

公开(公告)号：US11676880B2

公开(公告)日：2023-06-13

申请号：US15361399

申请日：2016-11-26

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Archana Venugopal ,  Luigi Colombo ,  Robert Reid Doering

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/367 ,  H01L23/373 ,  H01L21/48

CPC classification number: H01L23/3677 ,  H01L21/4882 ,  H01L23/3731 ,  H01L23/3733 ,  H01L23/3736

Abstract: An integrated circuit has a substrate and an interconnect region disposed on the substrate. The interconnect region includes a plurality of interconnect levels. Each interconnect level includes interconnects in dielectric material. The integrated circuit includes a thermal via in the interconnect region. The thermal via extends vertically in at least one of the interconnect levels in the interconnect region. The thermal via includes a cohered nanoparticle film in which adjacent nanoparticles are cohered to each other. The thermal via has a thermal conductivity higher than dielectric material touching the thermal via. The cohered nanoparticle film is formed by a method which includes an additive process.

公开(公告)号：US20220208640A1

公开(公告)日：2022-06-30

申请号：US17138541

申请日：2020-12-30

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Nazila Dadvand ,  Archana Venugopal ,  Daniel Lee Revier

IPC: H01L23/373 ,  H01L23/532 ,  H01L21/78 ,  H01L21/3205 ,  H01L21/683

Abstract: In described examples, a semiconductor wafer with a thermally conductive surface layer comprises a bulk semiconductor layer having a first surface and a second surface, circuitry on the first surface, a metallic layer attached to the first surface or the second surface, and a graphene layer attached to the metallic layer. The first surface opposes the second surface. The metallic layer comprises a transition metal.

公开(公告)号：US11254775B2

公开(公告)日：2022-02-22

申请号：US16229971

申请日：2018-12-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nazila Dadvand ,  Benjamin Stassen Cook ,  Archana Venugopal ,  Luigi Colombo

IPC: C08F292/00 ,  C08F8/42 ,  C08L33/12 ,  C08K3/08 ,  C08K7/00 ,  C08J5/24 ,  G03F1/78 ,  C08K3/04 ,  C08J5/00 ,  C08L25/06

Abstract: A composite material comprises a polymer matrix having microstructure filler materials that comprise a plurality of interconnected units wherein the units are formed of connected tubes. The tubes may be formed by photo-initiating the polymerization of a monomer in a pattern of interconnected units to form a polymer microlattice, removing unpolymerized monomer, coating the polymer microlattice with a metal, removing the polymer microlattice to leave a metal microlattice, growing or depositing a material on the metal microlattice such as graphene, hexagonal boron nitride or other ceramic, and subsequently removing the metal microlattice.

公开(公告)号：US20210118762A1

公开(公告)日：2021-04-22

申请号：US17114219

申请日：2020-12-07

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Archana Venugopal ,  Luigi Colombo ,  Robert Reid Doering

IPC: H01L23/367 ,  H01L27/02 ,  H01L21/3205 ,  H01L21/324 ,  H01L21/768 ,  H01L23/373 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: An integrated circuit has a substrate that includes a semiconductor material, and an interconnect region disposed on the substrate. The integrated circuit includes a thermal routing trench in the substrate. The thermal routing trench includes a cohered nanoparticle film in which adjacent nanoparticles are cohered to each other. The thermal routing trench has a thermal conductivity higher than the semiconductor material contacting the thermal routing trench. The cohered nanoparticle film is formed by an additive process.

公开(公告)号：US10811334B2

公开(公告)日：2020-10-20

申请号：US15361394

申请日：2016-11-26

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Archana Venugopal ,  Luigi Colombo ,  Robert Reid Doering

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/495 ,  H01L23/34 ,  H01L23/367 ,  H01L23/373 ,  H01L21/48 ,  H01L21/768 ,  H01L23/522 ,  H01L23/00 ,  H01L23/532

Abstract: An integrated circuit has a substrate and an interconnect region disposed on the substrate. The interconnect region has a plurality of interconnect levels. The integrated circuit includes a thermal routing structure in the interconnect region. The thermal routing structure extends over a portion, but not all, of the integrated circuit in the interconnect region. The thermal routing structure includes a cohered nanoparticle film in which adjacent nanoparticles cohere to each other. The thermal routing structure has a thermal conductivity higher than dielectric material touching the thermal routing structure. The cohered nanoparticle film is formed by a method which includes an additive process.

公开(公告)号：US10181521B2

公开(公告)日：2019-01-15

申请号：US15437818

申请日：2017-02-21

Applicant: Texas Instruments Incorporated

Inventor： Archana Venugopal ,  Benjamin Stassen Cook ,  Luigi Colombo ,  Robert Reid Doering

IPC: H01L29/16 ,  H01L29/66 ,  H01L29/778 ,  H01L23/66 ,  H01L49/02

Abstract: A microelectronic device includes an electrical conductor which includes a graphene heterolayer. The graphene heterolayer includes a plurality of alternating layers of graphene and barrier material. Each layer of the graphene has one to two atomic layers of graphene. Each layer of the barrier material has one to three layers of hexagonal boron nitride, cubic boron nitride, and/or aluminum nitride. The layers of graphene and the layers of barrier material may be continuous, or may be disposed in nanoparticles of a nanoparticle film.