公开(公告)号：US20230384820A1

公开(公告)日：2023-11-30

申请号：US17824695

申请日：2022-05-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Atul Ramakant LELE ,  Dirk PREIKSZAT ,  Gregory NORTH ,  Robin Osa HOEL ,  Tarjei AABERGE

IPC: G06F1/12 ,  G06F1/08 ,  G06F1/10

CPC classification number: G06F1/12 ,  G06F1/08 ,  G06F1/10

Abstract: Aspects of the disclosure provide for an apparatus. In an example, the apparatus includes a clock switching circuit coupled to oscillators and one or more circuit units. The clock switching circuit is configured to receive, from the oscillators, a set of frequency signals, provide an uplink primary clock signal and an enable signal to the one or more circuit units, the enable signal determined synchronously with the uplink primary clock signal, receive, from the one or more circuit units or a clock management circuit, a clock frequency request, provide the uplink primary clock signal based on a first signal of the set of frequency signals, and according to the clock frequency request, determining whether to continue to provide the uplink primary clock signal based on the first signal or on a second signal of the set of frequency signals.

公开(公告)号：US20250076918A1

公开(公告)日：2025-03-06

申请号：US18951807

申请日：2024-11-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Atul Ramakant LELE ,  Paul John PATCHEN ,  Ryan Alexander SMITH ,  Bernd Hannes SCHNEIDER

IPC: G06F1/12 ,  H03K21/02

Abstract: An electronic circuit includes an oscillator circuit, a first divider circuit, a synchronization control circuit, and a peripheral circuit. The oscillator circuit is configured to generate a base frequency clock. The first divider circuit is configured to divide the base frequency clock by a first selectable divisor to generate a divided clock. The synchronization control circuit is configured to generate a synchronization pulse that controls a change of the first selectable divisor in the first divider circuit from a first value to a second value. A pulse width of the synchronization pulse is based on the first value of the first selectable divisor. The peripheral circuit is coupled to the first divider circuit and the synchronization control circuit. The peripheral circuit includes a second divider circuit. The second divider circuit divides the divided clock by a second selectable divisor, and change the second selectable divisor responsive to the synchronization pulse.

公开(公告)号：US20230400878A1

公开(公告)日：2023-12-14

申请号：US18240052

申请日：2023-08-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Atul Ramakant LELE ,  Per Torstein ROINE

IPC: G06F1/12 ,  G06F1/06 ,  H04J3/06

CPC classification number: G06F1/12 ,  G06F1/06 ,  H04J3/0679

Abstract: A device includes a clock generator configured to generate a root clock signal based on an input clock signal and a clock generator divider integer setting. The device also includes a first component coupled to the clock generator and configured to generate a first component clock signal based on the root clock signal and a first component divider integer setting. The device also includes a second component coupled to the clock generator and configured to generate a second component clock signal based on the root clock signal and a second component divider integer setting. The device also includes sync circuitry coupled to each of the clock generator, the first component, and the second component, wherein the sync circuitry is configured to perform synchronized adjustments to the root clock signal, the first component clock signal, and the second component clock signal.

公开(公告)号：US20220334610A1

公开(公告)日：2022-10-20

申请号：US17857837

申请日：2022-07-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Atul Ramakant LELE ,  Per Torstein ROINE

IPC: G06F1/12 ,  G06F1/06 ,  H04J3/06

Abstract: A device includes a clock generator configured to generate a root clock signal based on an input clock signal and a clock generator divider integer setting. The device also includes a first component coupled to the clock generator and configured to generate a first component clock signal based on the root clock signal and a first component divider integer setting. The device also includes a second component coupled to the clock generator and configured to generate a second component clock signal based on the root clock signal and a second component divider integer setting. The device also includes sync circuitry coupled to each of the clock generator, the first component, and the second component, wherein the sync circuitry is configured to perform synchronized adjustments to the root clock signal, the first component clock signal, and the second component clock signal.

公开(公告)号：US20210034095A1

公开(公告)日：2021-02-04

申请号：US16527342

申请日：2019-07-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Atul Ramakant LELE ,  Per Torstein ROINE

IPC: G06F1/12 ,  H04J3/06 ,  G06F1/06

Abstract: A device includes a clock generator configured to generate a root clock signal based on an input clock signal and a clock generator divider integer setting. The device also includes a first component coupled to the clock generator and configured to generate a first component clock signal based on the root clock signal and a first component divider integer setting. The device also includes a second component coupled to the clock generator and configured to generate a second component clock signal based on the root clock signal and a second component divider integer setting. The device also includes sync circuitry coupled to each of the clock generator, the first component, and the second component, wherein the sync circuitry is configured to perform synchronized adjustments to the root clock signal, the first component clock signal, and the second component clock signal.